NI VeriStand Add-Ons Discussions

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Engine Simulation Toolkit Feedback

I've updated the Open Source section with the GitHub link, though it may take some time for these changes to be publicly available. Thank you for the feedback.

National Instruments
Senior Systems Engineer
Message 101 of 200
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Thanks!

Kind Regards,
Thierry C - CLA, CTA - Senior R&D Engineer (Former Support Engineer) - National Instruments
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Message 102 of 200
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Hi Stephen,

I am experimenting with the EST Tool kit.

I am using a PXI-R7852R for my FPGA Target.

I have the basic DIO signal used for Crank Cam working.

My next step was to integrate additional code to the EST FPGA VI.

The intention is to tap into the unused FPGA resource to generate Analog/Discrete Outs as well as PWM outputs.

For that I followed the tips you have given in the forum with regards to using the XML builder node and FPGA interface tool.

I have success in generating analog and digital out.

But I am facing some problems with the PWM out.

I have two controls in VeriStand that pass in Duty, Cycle and Frequency info the target.

The duty cycle works giving 0.3, gives duty cycle of 30%.

It's the Frequency that I can't figure out giving a value of 0.04 fives an out put frequency 142.857Hz.

My question is how does this werid scaling came about?

What actually gets passed to the target when I input 0.4 for frequency?

My reference for the PWM implementation is based on your Advanced PWM Example.

Appreciate your help. Thanks!

Cheers

Raymond

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Message 103 of 200
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Hello Raymond,

How are you configuring the channel in the FPGA XML Builder Node? The node requires that you set the Scale and Offset for each channel. This is handled in the XML (*.fpgaconfig file) of the Advanced PWM example you referenced. The scale for the frequency channels should be 40000000 (40 MHz) and the offset should be 0. The PWM frequency is generated using periods/tick. A "tick" is of the Single-Cycle Timed Loop clock. If you'd like details on how the scaling is handled in VeriStand I recommend viewing the Understanding Scale and Offset section of Creating a Custom FPGA Configuration File.

Best Regards,

Lynn

National Instruments
Senior Systems Engineer
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Message 104 of 200
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Hi Lynn,

You are right! I did not setup the channel scaling in the XML node. It is working now.

I am still getting familier with Labview and Veristand.

There is so much to learn!

Thanks again for the help, appreciate it.

Cheers,

Raymond

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Message 105 of 200
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We have just upgraded to VS 2014 and are switching over from the Eng Sim Custom Device to the Eng Sim Toolkit.  I can see how to export the digital patterns, but not how to import them.  Does this functionality still exist?  Also, it looks like the format changed, so are the patterns that we used with the custom device no longer compatible?

Thanks,

Matt

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Message 106 of 200
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Hi Matt,

Importing digital patterns is on the roadmap but is currently not implemented. However, it will be included in the next release.

Best Regards,

Lynn

National Instruments
Senior Systems Engineer
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Message 107 of 200
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Hi Stephen,

I am interested in programmatically creating system definitions in VeriStand using the .NET API. Is there an API for the EST?

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Message 108 of 200
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Hi aweiss,

At this time there is no API for creating system definitions programmatically. However, it can be accomplished with some work - mainly using the System Definition API and having an understanding of the XML for each piece of the custom device.

Best Regards,

Lynn

National Instruments
Senior Systems Engineer
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Message 109 of 200
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Hi Lynn,

Is there an existing custom device with an API that I can use as an example to get started?

Thanks,
Adam

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Message 110 of 200
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