Engine Simulation Toolkit Feedback

[Andy-C]

Hi orestegino,

I'm not sure if the EtherCAT RIO chassis (9144 or 9145) will work with the Engine Simulation Toolkit. My guess is no, but I've never tried it. My concern is that the EtherCAT chassis can only communicate data via User Defined Variables. The Engine Simulation Toolkit relies on front panel controls and indicators on the FPGA VI. The 914x do not have an FPGA host interface to update controls and indicators.

This custom device is now officially supported by NI. You can get support by either creating a service request (ni.com/support) or filing an issue on the source code located on GitHub: https://github.com/ni/niveristand-engine-simulation-toolkit-custom-device.

I recommend opening a support ticket or filing an issue to understand whether that chassis is supported. 

Best,

Andy

[User002]

orestegino,

I'll be the bad guy and say it.  Andy-C is right - there's no support for the EtherCAT chassis.  The reason is exactly what he mentioned - that the FPGA doesn't have a full, typical RIO interface.

One alternative option that works for some systems is a MXI-RIO chassis, such as the NI-9159.  I know, it has a different kind of interface, but if you can handle that change, I've seen it work in a variety of systems.

Regards,

[cbacchiani_ges]

Hi HandyAndy, I'm orestegino's colleague and I can answer WRT your valid point. Indeed we know about the 9159 chassis, and we're using exactly that in another similar simulator. The 9145 solution was suggested as an alternative since the 9159 has a quite old FPGA chip and there are no newer ones with MXI or similar.

[cbacchiani_ges]

For reference: I've finally found the GitHub project of the FPGA IP library, though it doesn't seem as recently updated as the custom device one.

It would be cool to add a link to EST's main page too.

[Rscd27]

Stephen B,

Thank you for the toolkit. I was unable to find a compiled version for VS 2017. I am attaching the one I am using, it may be useful for some other people.

[naktaaa]

THANKS, thats definately what my customer wanted! I informed him your post.

[naktaaa]

Hello Forum, This is NIK AE Specialist Jaehyung Chung.

I just recognized the FPGA adv. Session for LV 2018 is launched. So, I try to build Custom Device on LV2018, but I found 'Bad VI' when I execute mass compile the source code project. the Engine VI Template.vit in Engine folder is broken like below.

Is that ok to let this vitemplate file be in bad vi situation?

Best,

Chung, Jaehyung

NIK AES

[Donovan_B]

It is fine for this template to be broken. It is used as a starting point for other VIs in the engine, but is not supposed to be functioning code. It is not included in the compiled custom device.

[orestegino]

Hi everybody,

I am using a veristand project with the EST (Custom device version 1.3.2) on a PXI-7854R fpga (with a EST bitfile version 1.3.0). Everything works.

If I recompile the bitfile, when I try to deploy the project I obtain this error:

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
The VeriStand Gateway encountered an error while deploying the System Definition file.

Details:
Error -61206 occurred at Project Window.lvlib:Project Window.vi >> Project Window.lvlib:Command Loop.vi >> NI_VS Workspace ExecutionAPI.lvlib:NI VeriStand - Connect to System.vi

Possible reason(s):

LabVIEW FPGA: The configured item does not exist.
=========================
NI VeriStand: Engine Simulation Toolkit Engine.lvlib:Init Unused IP.vi:1640001

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

And it is code-independent: it's the same if I compile the same source of the previous working bitfile or if I compile a vi containing only the est.version block or whatever.

I tried the workaround suggested on the home page of the EST for the error -61205 (that looks similar) but no results. I also reinstalled the EST package but nothing.

Any suggestion?

Thank you very much!

OresteGino

[RapidEngineeringGroup]

Hello All,

I'm building up a setup to Provide Crank Hall 5V sinking to 0v  and CAMS 1-4 5V sinking to 0V and would appreciate some direction as I'm new to working with NI Labview and Veristand below is my setup

Is there a Guide or Manual available for this Custom Device as for setting it up?

PXIe-1062Q

PXIe-8108 RT

PXI-7853R

R-Chassis 9151 cabled to the PXI-7853R Connector 1 RDIO

Modules in the 9151:

Slot 1 NI-9477 <--- will this work or must I use say the 9401 ?

Labview 2014

Veristand 2014

What exactly will I need to get up and running for a 60-2 setup and what must I do for the PXI-7853R FPGA card to be used as the other example and posts use various FPGA cards.  If anyone has this up and running please Message me

Many Thanks in Advance