Engine Simulation Toolkit Feedback

[Joel-P]

Hello Ytochigi,

The problem is a localization error when LabVIEW converts the string constant to Japanese, the Custom Device itself doesn't do the localization changes.

We have a couple of options on how to fix the problem. The simplest solution is to manually change the string constant when this Custom Device is built in other languages.

We could also add a property node to read the property App.Language, and if this returns "ja" we could wire that into a case structure to use the correct Japanese text. I'm not positive this will work because the string returned from the app.language may not exactly match when it is called in a different language.

Another solution would be to change the string constant to a global variable with the text as default in the control. This would still require you to manually change the global variable text before building, but it keeps all the localization changes in a single global variable. I have seen this method used for localization of display messages before, however it would be difficult and tedious to move all of the strings to a localization global.

[Joel-P]

Hello cbacchiani,

You're right, the analog replay function is a bug, however I went to go look at the source code on GitHub, and that problem has already been fixed. Could you tell me which version of the VI Package that you installed, or did you get this from GitHub?

The other thing that we need to check is the Scale Constant that is wired into the Analog Replay VI on the top level FPGA VI that you're using. In this case, the scale constant needs to be -3 instead of the default -2 because we're using half the memory size.

Those two issues combined together would account for the doubled output streaming frequency. If we just had the crank/cycle bug, then we would only replay the first half of the analog replay data. If we only had the Scale Constant wrong, then we would display all the data (decimated by 2) in the first half of the Cycle. But with both of these we would have the full Crank Waveform displaying once every cycle, in effect doubling the output rate.

So the solution to this is to update the VI Package that you're using, and if you are up to date (1.3.0.36 I think), then that means that the VI Package hasn't been updated since the bug fix, and I can do that if needed. The other thing that needs to be done is to check the Scale Constant that is wired into the analog replay. Based on your description I think that this is set to -2, but it needs to be -3 when we are using half of the default memory size.

[Joel-P]

Hello cbacchiani, again (...I'm working backwards through the latest posts)

This is a good bug to catch, and I'm glad that you were able to get it working by configuring everything on the first APU. I believe this should also work on the digital pattern generation that your colleague Fefo was working on [Edit: Just saw that you mentioned that this worked]

You're right that the FPGA is going to link the proper APU's to the sub-modules of code, since they are all wired together to share the register bus. So this should work fine.

FYI, I posted this issue to the GitHub source code page.

https://github.com/NIVeriStandAdd-Ons/Engine-Simulation-Toolkit-Custom-Device/issues/4

[cbacchiani]

Hello Joel,

Thank you very much for taking the time of looking into those issues. I'll try to reply to both messages as best as I can.

Regarding the analog replay issue:

• my mistake of not reading into that '-2' input, I could have realized that by reading the context help better;
• I got the version 1.3.0.36 of the package from the Package Manager, I cloned the GitHub repository but as far as I could see it only contains the source for the custom device, not the FPGA library;

Also thank you for submitting the bug report on the other issue, just as a note it applies to all signal generations, not only analog.

[Fast_Moto]

I am relatively new to lab view and veristand, but I wanted to understand the architecture of the program better. Is there a reason you are using registers rather than global variables (used in earlier versions of the HIL software)?  Can the other modules use the angle written into those registers in the same clock cycle?  Or is there one clock cycle delay (or more) assuming all parallel structures use the same base clock?

these may be basic questions, but I would like to understand this in a bit more depth. Thanks.

[Chuan]

Hi,

I am new to VeriStand and EST. The overview says in NI VeriStand, simply load a LabVIEW FPGA bitfile that includes Engine Simulation Toolkit IP and configure the measurement and generation options. Combine with your own engine physics model to create a complete ECU hardware-in-the-loop system. 

I have two questions:

(1) What code(Engine Simulation Toolkit IP) should I write in the project which is used to generate the FPGA bitfile?

(2) Is the engine physical model something already in EST or something we have to code in LabVIEW?

Thanks,

JC

[michaelhalbout]

Hello,

I can not install a requires software LabVIEW FPGA Advanced Session Resources to compile the toolkit on veristand 2017

If I want built this toolkit, I have this error message

Has anyone compiled for this version?

[goldsgo]

Hello，i met with some problems when i deployment the custom device to NI hardware through Veristand. I tried in my windows PC, no problem, but in customer's Hil, there were some errors.

The Veristand version is 2013.

Is there somebody met with the same problem and can give me some advice?

[PJD123]

Hi,

We are using Engine Simulation Toolkit version "Engine Simulation Toolkit NIVS 2015 v1.3.2 Build v4", "VeriStand 2015 SP1" and 'LabView 2015 SP1" on a PXI System.

The PXI System contains,

PXIe-1071 Chassis

PXIe-8840 Quad Core Controller

PXI - 7854R FPGA

PXIe-6356 DAQ (recently added to Chassis)

Questions:

What is the expected PCL (Primary Control Loop) rate variation expected with the Engine Simulation Toolkit enabled?

We are running the PCL rate at 5 KHz. and the PCL variation with the Engine Simulation Toolkit enabled is 2.5 KHz. and about 500 Hz, when the Engine Simulation Toolkit is not enabled.

Another problem that started occurring after the PXIe-6356 DAQ was install is that VeriStand intermittently locks up with error code -200714 or -209801.  Is this related to the PCL variation?

Has anyone seen this problem?

Any help is appreciated.

Perry

[naktaaa]

Hello, EST Feedback forum

One of the customer uses EST custom device on NIVS 2015 with 7847R.

As you know the 7847R doesn't supported by 2015 FPGA compiler, so I suggest him to build FPGA bitfile on 2017 with est toolkit add-on for LV2017.

However he said the custom device on 2015 fails to change value on bitfile compiled on 2017.

Now he is asking us to upgrade custom device to 2017 because he is doubting on version compatibility issue.

Why does it happens? Is this really a compatibility issue between Custom Device on NIVS 2015 with bitfile on LV 2017?

Could also you compile custom device for NIVS 2017?

Best