Engine Simulation Toolkit Feedback

[Joel-P]

Hello NFT,

The initial build that I had posted was missing the VxWorks.llb which caused a couple weird issues with the dependent files for the other targets. I posted a new build on the Engine Simulation Toolkit Community Page (Engine Simulation Toolkit NIVS 2015 v1.3.2 Built_v2.zip)

1) I haven't looked into this yet, but it looks like it will be a minor bug fix for the source code since it wasn't originally developed or tested on the Linux targets.

2) I also ran into this, using a previously built project with the custom device would result in a deployment failure pointing towards the VxWorks .llb, despite this being a Pharlap target. I took a look at the sysdef xml and found that it was incorrectly attaching the VxWorks llb to all of the other targets instead of their correct llb's. I built a new project (once I had reinstalled the new custom device build), and this error went away.

I am unsure why the VxWorks llb was being listed as a dependent file on the other targets, I am looking into this now as it might be a bug with VeriStand when an expected llb is missing for a target.

As a quick example, this is the incorrect XML that I found in the system definition

<Property Name="Driver VI Path_2">

<DependentFile Type="To Common Doc Dir" Path="Custom Devices\Engine Simulation Toolkit\c\Engine Simulation Toolkit Engine Linux_32_ARM.llb\RT Driver VI.vi">

<Version>1.3.2</Version>

<ForceDownload>false</ForceDownload>

<RTDestination>c:\ni-rt\NIVeriStand\Custom Devices\Engine Simulation Toolkit\Engine Simulation Toolkit Engine VxWorks.llb\RT Driver VI.vi</RTDestination>

<SupportedTarget>VxWorks</SupportedTarget>

<MD5 />

</DependentFile>

</Property>

3) I ran into this issue with the build on my first build as well, there is a specific LabVIEW INI token that we need to set in order to build this custom device.

NI_AppBuilder_SDist_ExcludeEditTime=True

Adding that ini token to the LabVIEW ini file will fix the build.

[Joel-P]

Hello Claudio,

I think that you may have been running into the same issue that I addressed in 2) above. I just pulled open the 2015 build version and I can see that RT Driver VI.vi is included. I am not sure why it would not have appeared when you were looking at the built version. I would recommend that you download the new build from this morning and test deploying the custom device to a pharlap target in a new .vsproj.

[bneaves]

Having issues deploying a basic EST project using the 2015

Controller is PXIe8R880 running PharLap 13.1

FPGA is PXI-7852-R

NI EST 2015 v1.3.2 Build v2 (1.3.3 in zip file)

With the basic setup with no APU Custom device added the project deplays and runs

When I add the APU1 with the bitfile I have compiled i get the follwing error when deploying

The VeriStand Gateway encountered an error while deploying the System Definition file.

Details:

Error 7 occurred at Project Window.lvlib:Project Window.vi >> Project Window.lvlib:Command Loop.vi >> NI_VS Workspace ExecutionAPI.lvlib:NI VeriStand - Connect to System.vi

Possible reason(s):

LabVIEW:  File not found. The file might be in a different location or deleted. Use the command prompt or the file explorer to verify that the path is correct.

=========================

NI-488:  Nonexistent GPIB interface.

=========================

NI VeriStand:  Open VI Reference in NI VeriStand Engine.lvlib:Open Custom Device Driver VI Reference.vi->NI VeriStand Engine.lvlib:Launch Asynchronous Custom Device.vi->NI VeriStand Engine.lvlib:VeriStand Engine State Machine.vi->NI VeriStand Engine.lvlib:VeriStand Engine.vi->NI VeriStand Engine.lvlib:VeriStand Engine Wrapper (RT).vi<APPEND>

c:\ni-rt\NIVeriStand\Custom Devices\Engine Simulation Toolkit\Engine Simulation Toolkit Engine Pharlap.llb\RT Driver VI.vi

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

• Sending reset command to all targets...

• Stopping TCP loops.

Waiting for TCP loops to shut down...

• TCP loops shut down successfully.

• Unloading System Definition file...

• Connection with target Controller has been lost.

Interestingly in the project dependances list it shows "Engine Simulation Toolkit Engine Linux_32_ARM"

I see others have had issues witht he missing RT Drive.vi but i thought this was fixed in the Buildv2

Any help appreciated

[Thør]

One thing to quickly rule out is to make sure that you've also built the engine LLb for Pharlap.  Can you quickly verify that you've built this build spec in the custom device project?

Aside from that, without any APUs present, I'm not sure if the custom device even deploys the associated bitfile.... what bitfile are you using and where is it located?  Do you see it FTP'ing across in the deployment status window?

[bneaves]

Had a bit of a play around tonight, not totally sure how you have got tot he stage when you have "Engine Release" in the Build Specifications tree, I have tried various things

From the instructions i have been following I have not come across anything saying i have to expicitly select the build spec in the custom divice project, maybe this is some thing I have missed

Screen shot below of FPGA Bitfile lvproj and My main Veristand Config I am trying to deloy

[Thør]

Hey bneaves,

Sorry, I should have been more specific.  The screenshot I sent you was from the build specifications for the Engine Sim Custom Device itself, and not from the project you use to build your FPGA bitfile.  Did you build this custom device yourself, or receive it already built?  Just trying to rule out any simple build issues first.

Also, are you saying that you get error 7 when you have an APU specified, but not when you don't?  Wanted to double-check that it's the same error in both cases.

[bneaves]

Hi,

Yes both these projects have been created but they use standard settings and VI's. But for my specific hardware. I used the Everything.vi for the fpga

I only get the error 7 when I have an apu added, if I delete the apu the same project deploys and runs without error

Reading back above my issue does sound very similar to a previous poster with 2015

[Thør]

I also noticed in your most recent screenshot that you're using both the engine simulation toolkit and the built-in FPGA functionality.  Are these 2 entities using separate FPGA cards in the chassis, or the same card?  If it's the same card, you need to make sure you're using the exact same bitfile for both sections.  As far as I know, the "everything.vi" doesn't contain VeriStand's FPGA template.  Did you add that to the engine simulation example bitfile, or are these running on 2 separate RIO devices?

[bneaves]

OK, not intentional. Only one FPGA card

To create the project I did a search for hardware and it adds the main FPGA, I then just assigned the profile to it otherwise it complains

So should I delete the RIO0 section or the whole FPGA section?

[Thør]

Just the RIO0 section.  Has that rogue RIO0 been there the whole time, or is it just a red herring?