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Engine Simulation Toolkit Feedback

Hello,  At present, I work on Engine Simulation toolkit . I am in charge of the measure of injection time on an engine 4 cylinders. For that purpose I set a Measurement Windows in Event Timing. I have quetions about measuring range. For the cylinder 1, my measuring range is:  -Min Angle: 180     -Max Angle: 720     -Reference Angle: 720. and my Event 1,2,3 are: -Reference angle:720     - Default start angle: -90     Default end angle: -90.  Do you think this measuring range are right and how to configure the other ranges of measure?  Thanks for your help.  Best regards

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Message 151 of 200
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I have an application where the model requires the injection durations to be in seconds rather than milliseconds.  I tried to create a scale to apply to all 20 durations (4 cylinders * 5 pulses), but it appears that the channels are not scalable.  This forces me to create 20 calculated channels.  Would it be possible to release a version where all channels are scalable and faultable.

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Message 152 of 200
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Since upgrading to Veristand 2015 SP1 we hve had an issue when deploying new settings to the digital signal generation of crank and cam signals

If we change the pattern of the crank and cam signals and then redeploy, the deploy completes successfully the the FPGA card does not update its output, it continues with the previous pattern generation (the generation does stop during the deploy and then restart again, so the FPGA is reset during the deploy but it doesnt appear to take the new settings

The only way to update the digital pattern generation settings is to power off the PXI unit and then deploy after a cold boot

Veristand 2015 SP1 Windows 7 64bit

PXIe 8880

PXIe 7852r

Latest Build 4 of the EST

We have been in contact with NI support to see if its a 2015.1 bug, they have concluded it must be EST. If needed though all details of their investigation are on file as REF 7454260

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Message 153 of 200
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This seems like the FPGA isn't being stopped and then re-started in between the two deploys. The Digital Patterns are pushed down to the FPGA in an initial configuration step before the APU is started, once we've passed that initial configuration step we can't change the digital pattern without restarting the FPGA.

This also makes sense because the custom device doesn't explicitly stop the FPGA when it is shutdown, as far as I can tell.

I do not know when, or if, the custom device changed whether it stops the FPGA on shutdown (there is code in the RT driver to shutdown but it is disabled).

  • What version of VeriStand, and Engine Simulation Toolkit Custom Device were you using before?

  • Are you using this FPGA with VeriStand FPGA interface as well as the Engine Simulation Toolkit (EST) code, or is it completely used for EST?

Sounds like it would be useful to add an option to shutdown the FPGA when the Custom device is shutdown. This may not have been done initially because the FPGA could be being used by multiple custom devices, and we wouldn't want to shut them down if the EST errors out or some other reason.

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Message 154 of 200
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I confirmed the behavior that I was expecting. When the system definition is undeployed, for an FPGA that is soley being used for EST, the FPGA will continue to run. When the system definition is re-deployed the FPGA doesn't restart, initial values are sent to the APU (that is still running) which will reset position and speed. This tricked me up a bit because my digital signals would go high on re-deploy making it appear to reset, but this is just an aspect of the APU going to reset position, which I proved by modifying the digital patterns value at 0 degrees. I also tested this by adding my own initialization code that would send a digital line high for 10s before allowing the APU to start, and this line did not go high on re-deploys.

I can speculate that if we were doing EST as well as VeriStand FPGA interface then this wouldn't be an issue as VeriStand will reset the FPGA at the end of execution.

Message 155 of 200
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Yes this matched my experience, we are only using EST on the FPGA

We have previously run 2014 and 2015 successfully, only when going to 2015.1 has this become an issue

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Message 156 of 200
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Hi

Is there a fix for this issue yet?

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Message 157 of 200
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It seems there is more up to date code on GitHub that doesnt appear to have made it into a build on the main site, is someone able to create an up to date build?

As support appears to be drying up for the issues with this code we will be looking to go elsewhere if things dont improve, this is a real shame as a huge amount of effort has clearly been put into this very promising toolkit

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Message 158 of 200
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Hello bneaves,

This toolkit is open source and it's maintained by the community, whoever is using it for specific projects tends to update it as necessary. If you have specific feature requests that haven't made it into the toolkit there are a couple options; You can contact your local NI Sales representative and talk to them to see what can or can't be done, and who could help develop the features; or you can add the features yourself since it's open source on github. And of course it's always a good idea to post it here to see if anyone has run into the same issue or if anyone else is asking for a specific feature.

If you want me to help you get in contact with your sales representative, feel free to PM me and I can get the right person involved.

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Message 159 of 200
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Hi Joel-P,

 

Is this feature under development?

We are looking for this feature to use in our system.

 

In cycle speed variation for the APU based on number of cylinders, cylinder offsets, and % variation

  • Ability to switch to a different variation profile for a single cycle to simulate the speed profile of a misfire

Thanks a lot,

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Message 160 of 200
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