Scan Engine & EtherCAT Custom Device Feedback

[plist]

I am currently running a setup with VeriStand using a cRIO-9082 along with 2 ethercat chassis. I am wonderring if it would be at all possible to run purely custom FPGA on the 9082, and use the etherCAT add-on to recieve IO from the other chassis?

I realize that running both custom FPGA and the scan engine on the same cRIO would not be possible, but I was hoping that this would be possible.

Thanks!

Paul List

[StephenB]

Yes you can do that. You can also do mixed or "hybrid mode" on the local (9082) chassis to do scan mode on some slots and FPGA on other slots. If you use custom devices that access the local FPGA directly like the engine simulation, electric motor simulation, or sensor simulation custom devices... just add in the custom devices (including scan/ethercat device) and pick your local bitfile on the scan/ethercat page and on the other custom devices and you're good to go. If you have other data you want to come from your bitfile into NIVS not related to any custom devices (not engine sim or sensor sim custom device data) then you can use "user variables" in your FPGA code and the scan/ethercat custom device will read those variables into channels for you. With all of these techniques, I recommend clicking the "synchronize controller with scan engine" checkbox on the scan/ethercat main page so your single point data from the 9144s is sync'd to the NIVS primary control loop.

If you want to use the NIVS FPGA template for the local chassis' FPGA and just add the bitfile under Chassis -> Hardware -> FPGA... this is a little weirder because that interface/template FPGA is designed for single point data and without some advanced sync techniques this single point data will be out of sync with your EtherCAT single point data. So I don't recommend this unless you know what you're doing or you're willing to uncheck the "synchronize controller with scan engine" checkbox on the scan/ethercat main page

[plist]

StephenB wrote:

Yes you can do that. You can also do mixed or "hybrid mode" on the local (9082) chassis to do scan mode on some slots and FPGA on other slots. If you use custom devices that access the local FPGA directly like the engine simulation, electric motor simulation, or sensor simulation custom devices... just add in the custom devices (including scan/ethercat device) and pick your local bitfile on the scan/ethercat page and on the other custom devices and you're good to go.

Hey Stephen,

First off, let me explain what I'm doing exactly. I'm using DRIVVEN modules for some VVT phase calculations on my cRIO-9082 as well as several other modules which are purely reading/writing directly to the modules. I'm using custom FPGA synced through VeriStand similar to the Sensor Simulation model. The two 9144s I'm using are acting purely as distributed I/O, no custom FPGA is required.

I would love to seperate the custom FPGA (My Custom Device) and the I/O, so that I wouldn't have to deal with the FPGA if a module changes, or is added. But I'm a bit confused on how you are telling me to go about that. As I'm aware there are only 3 DMAs available on the cRIO-9082, yes? As such, how would I be able to use both scan mode and custom FPGA on the cRIO, as my custom FPGA is already using two DMAs. I won't even be able to compile the FPGA once I move the additional modules to the "chassis" section of the project.

Are you saying I should set all the "additional I/O" as user variables from the FPGA? If so I can probably just leave everything as a custom device.

Also, say I do end up running the Custom Device entirely on it's own, and the Ethercat add-on purely for the 9144s. As long as I am syncing my custom device the same as the sensor simulation, and I select "synchronize" for the ethercat chassis, should I be fine in terms of synchronization?

Thanks for the help!

[StephenB]

Ah thanks for the description.

For your use case I suggest setting up your LabVIEW project in hybrid mode so your modules that simply do IO can be handled by the scan engine are are flexible for module changes. Yes, you're correct scan engine uses two DMA FIFOs. Because of this, you can't use the NIVS FPGA template that also uses two DMA FIFOs in hybrid mode because that would be 2+2 = 4 > 3 = Error.

However, you can still get data back to RT from your FPGA without using additional DMA FIFOs by not using the NIVS FPGA template and instead using another technique.

You can use controls/indicators in your FPGA front panel and read/write them with the FPGA interface inside your custom device. I recommend the LabVIEW FPGA Advanced Interface Tools so you can change the bitfile without recompiling the custom device.

You can also get data back directly to NIVS channels if you read/write the data to user variables in your FPGA because the scan/ethercat custom device will read/write user variables directly to/from channels.

To compile a hybrid mode bitfile, set up your LV project with some slots containing a 9201 (any module works, it just turns on scan mode for that slot) under the chassis and then with some slots under the FPGA. Create and use any user defined variables as needed. Or you could use controls/indicators. Up to you, you can use either or both. If you use controls/indicators you could directly read the values in your custom device... if you use user defined variables you would need to map those values over to your custom device.

here is what a project looks like configured in this way. This is actually a 9144, but a local chassis is pretty much the same:

After adding this bitfile to the scan/ethercat custom device you see this. (again this is showing ethercat but its the same with local chassis):

and there is another "to fpga" section farther down off the screenshot.

For sync... if you're using this technique with some slots in scan locally and all expansion chassis in scan... then all your scan slots will be sync'd simply because they are all using the scan engine. So feel free to set the checkbox to true so veristand is sync'd to the scan engine and therefore sync'd to all your single point I/O on all the chassis.

[Kalin_T]

When using the Scan Engine and EtherCAT custom device on a cRIO, the specialty digital input capability is limited to Pulse Width Measurements in microseconds, Edge Counting, and Period Measurement. Frequency Measurement does not work as expected. Pulse Measurement in microseconds seems to be a little off. My test set up is the following.

cRIO-9075 with 9423 (Slot 1), and 9474 (Slot2). I am outputing a PWM Signal at 1KHz on DO0 (9474), and read the signal on DI0 (9423).

VeriStand 2011.1 with NI-RIO 4.1.

Test 1. DI0 (9423) is set to Counter Specialty Mode. Measurement mode is Pulse Width Measurement. If I set the Duty Cycle of the PWM Output to 1%, I read 10.8 uS; 1.3% results in a reading of 20uS, and so on. There is inaccuracy in the Pulse Width measuremetns. 

Test 2. DI0 (9423) is set to Counter Specialty Mode. Measurement mode is Frequency Measurement. Frequency timebase is 256uS. The measurement that I see is 3.9. 3.9 x 256uS = roughly 1000 uS which is the period of the PWM. My expectation is to see 1KHz since I am in the Frequency Measurement mode. If I change the Frequency timebase to 512uS, then I measure 2. 2 x 512uS = roughly 1000 uS and so on... Also the measured number changes between 0 and that number (3.9 and 2 with my setup). It does not stay stable.

Test 3. DI0 (9423) is set to Counter Specialty Mode. Measurement mode is Period Measurement. Measure 1000 uS, which is expected. This works correctly. It can be used to calculate Frequency. 1/Period.

Any chance to address the concerns in Test 1 and Test 2?

Thanks.

KT

[Devin_K]

Hi Kalin,

I don't do any calculations in the code for the specialty digital functionality.  I just configure the module, and return what the read API returns.  So if there's a problem, I expect it's on RIO's end, not something specific to the custom device.

For test 1, I expect that the problem is the resolution of the module.  Since both the 9423 and 9474 only have a 1us update rate, it's not surprising that a 1kHz duty cycle isn't extremely accurate.  I wouldn't expect a duty cycle of 1.3% to return 20us though, so I'm not sure what's going on there.  It's probably something that should be tested in LabVIEW.

For test 2m the 256 uS frequency timebase should only be used to measure signals of 500 kHz or higher.  Even with the maximum timebase of 32768uS, you should only try to measure signals of 3.9kHz or higher.  So it's not surprising that a 1kHz signal returns weird results.  This isn't directly documented in the custom device, but it is in the C-Series help for speciality digital.  For signals slower than 3.9kHz you should measure the period, then take the inverse for the frequency (similar to your Test 3 above).

Regards,

Devin

[MaximeD]

Hi Stephen,

Concerning the error -2147138275 I had a few months back, I found out (with the help of the distributed system manager) that the problem came from my FPGA code. One of my while loops was not timed, and somehow Veristand could not manage to get the values of the UDVs in that loop.

Now I get another (quite similar) error while deploying a system with FPGA code on an etherCAT chassis. When I deploy my system with this code (see attached VI "FPGA_V62" and associated bitfile) on the etherCAT I get error -2147138277 : "A mismatch was found between user-defined variables deployed and running on the slave FPGA."

When I get this error code I have to restart cRIO and download a working FPGA (attached "FPGA_V10") to make the deployment successfull.

My problem is I do not understand why my FPGA code is wrong, and I need some help on that point.

Thanks for your time.

Regards,

Maxime

[StephenB]

Hi MaximeD,

I've seen this same error before when changing a working bitfile's variables. I'm not sure what causes it, but I was able to work around it by:

1. Download the new bitfile with the system explorer
2. Reboot the master
3. Reboot the slave
4. Deploy

Try that. If that doesnt work, try the steps in the troubleshooting section of NI VeriStand Add-On - Scan Engine and EtherCAT

[MaximeD]

Hi StephenB,

Thank you for your help, your first solution worked for me.

Maxime

[plist]

Hey Guys,

I'm loving the custom device but I have a couple of questions for you.

1. How hard would be it to allow one of the Ethercat slaves to be "Disabled". As it is now with the way VS works, it is very hard to run a system that has multiple chassis. It won't deploy if it doesn't see a specific chassis, yet deleting it breaks your entire system explorer configuration.

2. Along the same vein, how is it that a chassis can not be seen and the config will not deploy to the controller. Yet if communication is broken with one of the devices (or they are showing an error) the system still deploys?

The second one is probably due to my limited knowledge of the intricies of EtherCat, and what the error on the controller actually means. But I can sometimes deploy and have a chassis not responding, yet have no indication other than the light on the chassis itself.

Thanks for the help guys!