Scan Engine & EtherCAT Custom Device Feedback

[Damien21]

Hi,

I built a FPGA Personnality for the custom device.

The FPGA is load whitout errors in the custom device.

But when I deploy the sdf, I have the 537707 error.

This error is about the UDV container. I think I use there correctly.

I join my LabVIEW project.

If someone can help me it will be great.

[Andy-C]

Hi Damien21,

There are a couple of references to this error on the custom device community page:

http://forums.ni.com/t5/NI-VeriStand-Add-Ons-Documents/NI-VeriStand-Add-On-Scan-Engine-and-EtherCAT/...

<4.1.7>
Added a new control on the main page of the custom device to work around an NI-RIO issue. In RIO 13.0 through 14.1 (fixed in 15.0 when it releases), user defined variables do not appear immediately after loading a bitfile to a local chassis. The delay varies depending on the CPU power of the target system. If the scan engine devices proceeds as normal after loading the bitfile, error 537707 can occur indicating missing UDVs. Therefore, this new control allows a user to specify a delay to insert after loading all local chassis' bitfiles. It has no effect if no local chassis bitfiles were loaded.

Have you tried increasing the Delay control value on the Main page of the custom device configuration?

[Damien21]

Thank you for your response.

I have already read all the references to this error.

I tried to increase the delay but the result is the same, error 537707.

I use Veristand 2015 SP1 and a cRIO-9067 on linux32

[Andy-C]

One thing I noticed is the example project you included does not have any modules in the project configured in Scan Mode. I'm not sure what I would expect in this configuration. Have you tried using a bitfile that included both a module in Scan Module and a module in FPGA mode? If you aren't actually using the Scan Engine to access modules in Scan Mode then you could consider using other methods to access your FPGA variables - for example the open-source FPGA Add-on (https://github.com/NIVeriStandAdd-Ons/FPGA-Custom-Device) or VeriStand's native FPGA interface framework (http://www.ni.com/white-paper/9349/en/). 

Is there any other DAQ hardware in your system definition? 

How is your Chassis master hardware synchronization device configured? 

How is Primary Control Loop Timing Source configured?

Best regards,

Andy

[Damien21]

I add the other modules in the project.

I post the LabVIEW project and the VeriSTAND project.

The delay after load fpga is 30s

[JohnBergmans]

Hi.  Are there any plans to release the Scan Engine & EtherCAT Custom Device for VeriStand 2017?

-John

[Andy-C]

@Damien21, sorry for the delay getting back to you. Are you still struggling with deploying the Scan Engine & EtherCAT CD? As a test I was able to deploy  successfully to a cRIO-9068 with a simpler FPGA bitfile and a single Boolean UDV. I had two 9401s in Slots 1 & 2 in FPGA and Scan mode respectively. I was able to run with either Automatic PCL timing or Custom Device Timing based on the Scan Engine CD.

[Andy-C]

@JohnBergmans,

We are working on getting the 2017 build onto the Community download page. We'll update you guys here once it's available.

Best regards,

Andy

[JohnBergmans]

@Andy-C 

Thanks.  Is there a link to download VeriStand 2016 while waiting for the VS2017 version of the EtherCAT & Scan Engine CD?

-John Bergmans

[Andy-C]

John,

I found this link from ni.com/downloads : http://www.ni.com/download/ni-veristand-2016/6283/en/

Let me know if that doesn't work for any reason.

Andy