VeriStand FPGA XML Builder Node Feedback

[Ryan_S]

Hey Joshe,

From looking at the XML and error code, VeriStand is stating that it doesn't support the plus/minus sign (±) that you've used in a couple of your channels:

Unfortunanatley, it looks like the error was cascading down to other channels so it's not as obvious from the XML lines it provides in the error. If you remove the special character from the names of those channels (and any others) and re-generate the XML, it'll load into VeriStand without issue. I tried it on my end with just one channel and reproduced going from an error to working state.

--Ryan_S

[joshe]

Looks like we both figured it out.  I was just about to post the same thing.  Thanks for taking the time to help on this!

[Tosicka]

Hi VeriStand FPGA XML Builder Node developers,

in the first step I would like to thank you for FPGA XML Builder Node. It´s very useful tool.

While I was using FPGA XML Node I've two bugs which I would like to report.

1) When I wanted to create config XML with 0 elements in Write DMA and use it in VeriStand, I got an error. And also something very similar happened when I used about 200+ input/outputs mostly bools and u32. (LabVIEW 2015, VeriStand 2014, FPGA XML Builder Node 12993)

2) When I double click on FPGA XML node, inputs and outputs configuration windows is shown. In this windows are scale, offset etc. When I'm using mouse for selecting elements in signals tree structure then everything works well. But when I'm using arrows on keyboard for movement in signals tree structure then there is no refresh for selected signal offset, scale etc and the last values are displayed. It looks like there is missing event handling for selecting signals with arrows.

I hope this info will help you with Node improvement.

Best regards

Tomas

[HervéM]

Hi everyone,

I'm using this usefull tool to control some FPGA.

I have already use this add-on to transmit data for specific signal to Flex rio FPGA without issue.

Now, I want use it only for control some compact rio's Input and output.

All ports, digital and analog, are well-configured but some data are mixed, for example in veristand, I can find the data from the digital input port 1 of the 9425 card where I should find the data form the port 2.

Do you how fix this issue ?

You can find unclose my veristand and labview FPGA projects.

Best regard

Hervé

[Ryan_S]

Hey Tosicka,

Thanks for the feedback! To address your points:

1a. Error when using 0 elements in Write DMA - This is expected behavior and is defined by NI VeriStand, not this node. You would encounter the same behavior if you tried to send 0 elements through the Write DMA by creating the FPGA and XML manually. This is expected because VeriStand uses the DMAs for timing and blocks execution based on expecting to write and read at least 1 element on each DMA, and thus will throw a configuration error if you try and define a bitfile without one of the DMAs.

1b. Error with 200+ input/outputs mostly bools and u32 - This I wouldn't expect. Can you attach the FPGA code and XML file that reproduce this?

2. I took a peek and we're watching for value changes of the tree which I'd assumed would catch mouse clicks and keyboard moves, but maybe not? I'll add it to the list of items to investigate further.

Thanks! --Ryan_S

[Ryan_S]

Hey HerveM,

I haven't had a chance to look into how the node is scripting your particular backend communication, but my guess is that there's a bug in how it's packing or unpacking your data. I'd recommend you look at how the data is being packed/unpacked by looking at the "VeriStand FPGA XML Scripted Code.vi" that the node will have saved in your LabVIEW Data directory (defaults as <My Documents>\LabVIEW Data). If you identify the issue, you can fix it manually then copy and paste that code in place of the node and continue to use the XML that was generated. I know this sounds manual, but it's likely your fastest method to get running.

Hope that helps! --Ryan_S

[AOmar]

Hi Ryan_S,

I want to control frequency and duty cycle generating PWM, I'v read your Huazy responce, but i still not understand how can i control the frequency without changing the periode of the timde loop.

Thanks

[Ryan_S]

Hey AOmar,

Ok, well we provide examples (in <LabVIEW>\examples\NI VeriStand Add-On-FPGA XML Builder Node) that have code for generating and reading PWM signals. Have you looked at those?

In general, the way we perform PWM outs with VeriStand is as follows:

1. Add a PWM channel to the DMA FIFO (per the fpgaconfig XML file). This tells VeriStand to add two channels within your system definition file for that PWM Out; a frequency channel and a duty cycle channel. Behind the scenes, VeriStand then uses the values you write to these channels to calculate a high time and a low time (in ticks, based on the base clock, usually 40MHz) for a single period of the PWM. These values are sent down to the FPGA as a packed U64 (where 32 bits are the high time and 32 bits are the low time).

2. On the FPGA this high time and low time is read from the DMA FIFO and sent to a local variable. That control for that local variable is inside a Single Cycle Timed Loop, meaning it executes once per tick of the base clock. So, if we know how many ticks to be high and how many ticks to be low (by splitting the U64 into our 2 U32's for high and low ticks), each tick of the timed loop we just check should we be high or should we be low. This is a common approach for performing PWM out on FPGA.

On a side note though, keep in mind that #2 is simply the way we've chosen to do it on the FPGA. Technically, you can choose to generate the PWM signal however you like. VeriStand is sending down the high and low time in ticks, so you can use those values however you like to generate the PWM. The Single Cycle Timed Loop is the most efficient, but by no means the only way to accomplish the functionality.

Hope that helps! --Ryan_S

[StephenB]

By default veristand doesn't allow you to control the frequency. Just the duty cycle. See this example of how to fool veristand into letting you do so https://decibel.ni.com/content/docs/DOC-16699

[Ryan_S]

Ah, right, I was swapping FPGA PWM In/Out capabilities with DAQ PWM In/Out capabilities in my head. That'll teach me to write a response without opening the code...

AOmar, the example in the link Stephen posted implements #1 that I described above since VeriStand natively only lets you set the frequency during configuration for PWM Outs.

Appreciate the post Stephen!