VeriStand FPGA XML Builder Node Feedback

[StephenB]

My pleasure

Using this for the first time in a while. If you didn't know, there is a bug if you only have digital values flowing through the node. It pukes on code generation with this error:

Error: 1055

Error Source: Property Node in Create and Wire Index for Unpack Booleans.vi->Boolean Outputs for Index Array.vi->XNode_BuildAction.vi->FPGA XML.xnode:GenerateCode.vi->FPGA XML.xnode:GenerateCode.vi.ProxyCaller

Workaround is to add a int as well

Also, any chance the cant-have-same-names issue will get fixed? Thats really annoying

Thanks

[Ryan_S]

Yeah, I thought I'd added that to the known issues list, but apparently not. I just updated it.

The two major items I'm currently scoping for possible dev time are:

1. Re-writing the back-end code generation using the Code Gen Engine. There seem to be a couple scripting issues (including the boolean issue) hiding in the current VI scripting code. Hopefully switching to the code gen engine will simplify the backend stack and resolve these issues.

2. Re-writing the tree display to better handle section and channels names. This is lower on the list than Code-Gen since the work-around is simpler, but I also understand that it's very annoying.

I'm still in the scoping phase for these, so unsure what (if any) timeline would look like.

[AOmar]

Hey Ryan,

I thank you both Ryan and Stephen for the interest have giving to my demand, after your explanations i undertand very well the frequency and ticks Fpga relations and duty cycle.

I found the Project example that you refered to me in NI Veristand Xmlbuilder node, So i did th same thing with my project i just added a Pwm output on my xmlbuilder and the timed loop genrating Pwm with a local variable In my Source Code FPGA (attached pic) , i save my VI i compile my project Fpga, after few 30 minutes the compilation fails showing the error as you can see on th attached picture.

Have you any idea about the error reason, there is any configuration to do somwhere. i want also to know if the generatin or reading PWM only works with D I/O or with other modules works as inputs(NI9425) or only outputs(NI9475), with the A I/O.

Just for information my project consist to drive an Engine simulation Toolkit which run on a MXIRIO 9159 as FPGA target, withe a Veristand Engine runs on PXI Controller.

Any helps or solution will be really appreciate 

Best Regards

[AOmar]

[AOmar]

[Ryan_S]

Hey AOmar,

I mis-spoke in my original reply (prior to Stephen's) when I referenced the example that installs with the node. That example will allow you to output a PWM, but will still only let you set the frequency during configuration and not on the fly. I'd recommend going over and implementing the example that Stephen links in his post so you can modify the frequency at run-time.

If you still get errors at that point then please post back with code.

Hope that helps! --Ryan_S

[StephenB]

It would be super nice if I could remove an item from the middle of the list (either through clicking the node or by opening the dialog and deleting the channel)

[Ryan_S]

Agreed. Adding/removing elements of the node via right-click has been a feature request since we first completed the node.

Unfortunantly, it's always been lower on the priority list than other features/bugs. It's also, unfortunantly, not trivial to implement

[佳]

Hi Ryan_S,

When I use "FPGA XML Builder Node" configuration PXI-7811R(Connect0 0-39 DO;Connect1 0-39 DO;Connect2 0-9 PWM OUT, 10-14 DO;Connect3 0-22 DI,23-39 DO).I can't run the Vi for a unexpected error.Annex is the Vi.

Looking forward to your reply.

Best regards

Ning

[Ryan_S]

Hey Ning,

That's interesting. I'm wondering if this is either a back-end language issue or an issue with the DIO (we have seen some DIO bitpacking issues).

If you create a new VI and configure it with just a couple inputs (try it with all DIO as well as a mix of DIO and analog) do you still see the issue? Can you upload the simplified VI if it does reproduce? That way it's less backend scriped code to look at

Thanks! --Ryan_S