Forcing use of 10 MHz REF IN on a PXIe-1065 Chassis

[LabVIEW_Wizard]

I'm currently using a PXIe-1065 Chassis with a "PXIe-5663E Vector Signal Analyzer" & "PXIe-5673E Vector Signal Generator" (in addition to some other SLOT Cards).  I need a CLK Source with <100ppb so I purchased an external 10MHz CLK.  I am able to connect the 10MHz CLK to the back of the Chassis and then set REF_CLK_Source in the niRFSA & niRFSG Code that I have written.

Everything works great but if I unplug the external 10MHz CLK the Chassis continues to operate using a "Backplane generated" 10MHz CLK (See Table 1-2. Backplane External Clock Input Truth Table in NI PXIe-1065 User Manual page 1-13).  I do not have anything connected to the PXI_CLK10_IN pin in SLOT 14 of the Chassis.

I'm worried that if the external clock is unplugged or a cable is damaged that LabVIEW (and me) will never know and the equipment will continue making measurements using the less accurate CLK.  I would like the equipment to give me an ERROR when the 10 MHz REF IN is not driving the PXI_CLK10 signal.

i.e. How can I tell if the "Backplane generates its own clocks" through LabVIEW Software?

Somehow the Chassis knows and either drives the "Backplane generated" CLK Signal or leaves the 10 MHz REF IN to drive the signal.  If the Chassis can know then why can't I know?

[A_Donfigulation_Error_Has]

Hi LabVIEW_Wizard,

I have found 2 archived Knowledge Base articles about this topic and both of them indicate that there is no way for the software to know whether or not the PXI_CLK10, PXIe_CLK100 and  PXIe_SYNC100 are all phase-locked to the 10 MHz REF IN or to the PXI's internal 10MHz Clock. The reason why is because the override of the backplane clock when you provide the external 10 MHz clock is all handled directly through hardware circuitry on the PXI backplane. (Unfortunately you will not have access to these archived Knowledge Base articles as they cannot be viewed publically.)

Furthermore I have checked the schematics of the PXI backplane for the 1065 and have traced the 10 MHz REF IN enable line to a CPLD on the backplane. It is unclear from the schematic that I have found how this enable line is actually enabled and if there was anything built into the circuitry to give the user the ability to monitor which clock source is being used. 

I would like to take some extra time later this week to consult someone from R&D if there are any other workarounds but from what I have found so far, the answer seems to be "No", you can't really do anything to determine which clock is being used. The best thing you can do for now is to make sure that your external clock is plugged in correctly and is working properly. However, I think that if your external clock was receiving some clock signal that is out of spec (due to disconnection or a loose wire) while running a task then you will receive a "unable to PLL" error.

Jason L.

[A_Donfigulation_Error_Has]

Hi LabVIEW_Wizard,

I have finally talked to someone in R&D about this topic. It turns out that our developers did not write anything in such that you can monitor which CLK is being used. This issue has come up in the past before with someone also concerned that their external clock being used would cut out every once in a while. The solution they used to verify when this would happen was to attach a scope to the 10 MHz REF OUT BNC on the back and to compare it with the external signal being routed into the PXI chassis.

Jason L. 

[Henrik_Volkers]

 just a quick shot 😉 thinking of a 74LV4046 from Texas Instruments to compare Clock in and clock out ?