HSDIO 6555 trigger timing

[Mar1]

Hello,

I would like to get some information regarding the HSDIO trigger latency for acquisition task. 

When a trigger signal is received (from PFI0 for instance), does the acquisition start on:

A) The next rising edge of an internal board clock (fix 200MHz?). If this is the case, then this means that the next sampling (say 1MHz) should be aligned with that next 200MHz clock. I have doubts that this can be possible

or

B) The next sampling clock rising edge (say 1MHz), which means that the trigger latency can be anywhere from 0ns to 1us depending on when the trigger arrives wrt to the sampling clock.

This will also mean that the trigger latency depends on the sampling clock.

Thanks in advance,

Mar1

Thanks.

[santo_13]

The answer to your query is provided in the specifications document.

Though this was given for digital data output, I would assume the same for data acquisition since it was not explicitly mentioned in the document.

[Mar1]

Hi Santhosh,

Thanks for your answer. 

I will try to confirm your assumption.

Marwen.