NI 5761 with low sampling rate

[x_ni]

Hi,  is it possible to change the NI 5761 sampling rate without programming FPGA? Thank you very much!

[Josh_B1]

Hi x_ni,

The 5761 has a few options for what sample clock you use. If you are just using the internal clock as the sample clock then it runs at 250 Ms/s. If you want to use a different rate then you would need to use an external sample clock. Page 6 of the following manual explains this in more detail.

http://www.ni.com/pdf/manuals/375509a.pdf

Regards,

Josh B

[DLR_Arthur]

Hi

Actually, we got a similar problem here. We would like to use the NI5761 (with 7966R FPGA) in two different modes (i.e. two different sampling frequencies) which can be steered by the host-program. This means, at one setup, the sampling rate should be 215MHz and at another setup 200MHz. We will use the external reference of the IO Module in coupling with the DStarA line (using the NI-6674T timing card) but how can we arrange the two setups in Labview FPGA? For sampling, we use the "IO Module Clock0" which is compiled for a single frequency of 215MHz (setup 1 of our configuration, properties of the clock). Would it be enough to compile this for a range frequencies ranging between 175-250MHz? Is this the right way?

Thanks'

Regards,

Arthur

[alcava.cr]

Hi, as mentioned above you can play with the sample rate by using an external Sample clock. Take a look at the picture attach for the general idea. Simply replace the Boolean buttons for digital input ports. I hope this helps