PXI 7831R problems with changing lines from In to out

[LockheedJoe]

I have a PXI 7831R card and I'm doing a wrap back (for a selftest) from one port on a connector to another port. Connector 1; Port 0 to Conn 1; Port 1. I send a pattern out on port 0 and receive it on port one, it works. I then change port 1 to Ouputs and use port for input. I send out the pattern and it isn't wrapped back. On the 2nd or 3rd try it will work. (i.e. I send out 0xAA get 0x02, I then send out 0xAA and get 0xAA back)

This same wrap back works correctly on Connector 2 ports and the DIO ports of connector 0. It also works on all connector/ports of a PXI 7813R I'm using.

Has anyone seen this before? What do you do about this? What am I missing?

I've tried putting a delay between where I set a port as Output and actually dot the send. And I have a delay between where I send from one port and receive on the other port.

[Brinoceros]

Hi Joe,

Can you post a simple example VI that gives you this behavior?

[LockheedJoe]

the attached file has the project and vi's.

I usually run it from TestStand. This is a case structure where I send out a byte and read it back from another port. As you sequence through the tests from 1 up, tests 4,511,13 fail when you put a non-0 value as FPGA input (I start with 0xAA). when you sequence through by hand, if you repeat the test that fails, it passes the 2nd time.

Thanks for your help

Joe V

[Brinoceros]

Hi Joe,

Can you strip this down to just the case in question?  It really helps if we can completely isolate things, and make sure it is not a problem with the sequence of tests.  When you say sequence through by hand, are you just running the test twice from TestStand or from the actual project?  If you run this from the project, does it fail the first time?

Regards, 

[LockheedJoe]

It will be tomorrow (Friday) before I can do that I've been "redirected" for today.

[LockheedJoe · Accepted solution]

I found my problem. In a few of the case structures I had wire connected to the wrong place. They were just hidden by other structures in the diagram. It was just a coincidence that they happen to be on the cases where I was turning the inputs to outputs.

Labview 8.6 might of helped with the clean up diagram feature. We're using 8.5 since that's what we started with.

Thanks for your help

Joe V

[Brinoceros]

Glad to hear you found the problem.  And I would say 8.6 certainly could have helped.  The clean up block diagram feature is powerful.

[LockheedJoe]

Yes, 8.6 diagram clean up would have been nice. But when we start a project with a version we use it until we're done. In this case, 8.5

Thanks