PXI-7854R I/O pin state when bitfile is reloaded

[bwv1043]

PXI-7854R has Virtex5 FPGA.  I use some of the FPGA pins as digital output pins, either set to high or low states.  If I load another bitfile (either the same or different) then what is the expected behavior of the digital output pins?

Xilinx references indicate that it can be configured by setting HSWAPEN to enable or disable (by pull up/down).  How does PXI-7854R configure HSWAPEN pin?  Is this accessible to the user?

[crossrulz]

For most of the FPGA DIO pins, the default is to be an input.  This is usually the safest.

[bwv1043]

So do the digital I/O pins become Hi-Z input pins during loading of bitfile in PXI-7854R?  I understand the general guideline but I'd like to know exactly what PXI-7854R does, i.e. during power on reset, before and after configuration.

[Blizzard]

Hello,

You will be able to configure DIO lines to a specfic power-up state using an FPGA startup VI. 

This KnowledgeBase article below should be very helpful in creating a startup VI and configuring your DIO lines.

How Do I Set the Power-Up States of My 78XX R Series Device? :http://digital.ni.com/public.nsf/allkb/CB2F146DB6B56D29862572640073B57D

I hope this helps!

Regards,

Anna L