PXIe-6733 using chasis PXI CLK10 as reference clock

[LDParg]

Hello,
I'm working with a PXIe-1062q Chassis. I've connected a 10 Mhz reference signal in the rear panel "10 MHZ REF IN" of the chassis. How can I set up the PXI_CLK10 as the reference clock in the DAQ PXIe-6733?

I can see in the Chasis manual that the PXI_CLK10 is distributed in all slots.

I saw in the manual that i have to use the RTSI bus. In that case, the pag 14 of the 6733 manual says that the RTSI Clock is the PXI trigger (7) bus.

In labview, I can set PXI_trigger_7 as the 6733 Source of the master timebase, but i can`t route the PXI_CLK10 to the PXI_Trigger_7, so the master timebase of the DAQ continues being the internal board clock (20MHZ CLK).

[santo_13]

No need to do all those, just configure the reference clock

Why this would work

• 10MHz reference clock is used to derive the 100MHz PXIe clock in the backplane
• Onboard timebases of 6733 are synchronized with PXIe_CLK100 by setting it as a reference clock
• Now, onboard clock/timebase -> PXIe_CLK100 -> PXI_CLK10 (external)

This is how the whole system is referenced to the external 10MHz input

All these synchronizations are done at the hardware using PLLs.

[LDParg]

Thank you very much for your answer,

I Tryed whit your solution, but I have problems:

Am I doing something wrong?
I attach the VI

Regards, 

[santo_13]

I was going through the user manual, your 6733 is a PXI version and not PXIe, this means, only PXI_CLK10 is available and not the PXIe_CLK100

Moreover, I could not find any information about a configurable reference clock for your device which makes me suspect if it even supports such a feature.

My understanding of the PXI architecture is that the PXI_CLK10 and PXIe_CLK100 are routed to each card on a dedicated line apart from the PXI_Trig line or RTSI, this means the PXI_TRIG7 based Clock source is used only if some other instrument exports its sample clock or timebase and you cannot route PXI_CLK10 onto PXI_TRIG7.

Looking at available device routes for PXI-6733, there is no sign of PXI_CLK10 reference clock source

Whereas other instruments have such an entry, for example PXI-6229 and PXIe-6368

Based on all this information, I don't think this device can directly discipline off the 10MHz reference clock, however, if you have another instrument that can discipline off 10MHz reference clock such as 6368 then you can discipline that card to 10MHz and export its timebase/sample clock to this 6733 (over PXI_Trig7).

[LDParg]

Thanks for the feedback!

In your last answer you said: "Based on all this information, I don't think this device can directly discipline off the 10MHz reference clock, however, if you have another instrument that can discipline off 10MHz reference clock such as 6368 then you can discipline that card to 10MHz and export its timebase/sample clock to this 6733 (over PXI_Trig7)"

So, I have a 6674T board in the chassis. So I tried to route the PXI_CLK10 to the PXI_Trig7, using the NI MAX, but I've received the following message:

 

 

I'll appreciatte your help because I don´t see what I'm doing wrong.

[santo_13]

I should have been more specific, the other instrument has to be a DAQ with a supported route to export sample timebase to PXI_Trig7

For example, 6229 DAQ routes say that you can route the timebases to PXI_Trig7

I don't know if 6674T has such a supported route - please refer to the user manual to know if it is possible

[LDParg]

According to the 6674T manual, it's possible to route PXICLK10 with PXITrig7.
In the lower part of the figure, we can see a footnote: "Routing PXI_CLK10, PXIe_CLK10, OCXO or ClkGen is accomplished by setting the synchronization clock (using the NI-Sync Property Node) to the desired clock source and then routing the synchronization clock as the source". 

Also says: "Route through the FPGA"

I have the NI-Sync Property node in my labview, but I don´t undestand how it's implementend. I'll appreciate your help. 

I tried with the test panel, but indicates error

[santo_13 · Accepted solution]

You routed the PXI_CLK10 to SYNC but did not route the SYNC to PXI_Trig7 instead you again tried to route PXI_CLK10 to Trig7 - that was the mistake.

I tried this and no error

Please remember to set \66774T\PXI_Trig7 as the timebase/sample clock source

Curious, why do you need an External 10MHz input when you already have a 6674T with OCXO?? Is your external 10MHz ref is better than 6674T?

[LDParg]

Thanks four your help, finally the VI works and the 6733 is using the PXI_CLK10 as time base.

your answer :"Curious, why do you need an External 10MHz input when you already have a 6674T with OCXO?? Is your external 10MHz ref is better than 6674T?"

Sometimes I use the 6674T as a Time Base, locking the PXI_CLK10_In with the DDS 10 MHz signal. But sometimes I need to use the 6674T DDS for clocking (with other frequency) an external board, so in that case I lock the chassis with an external 10 Mhz reference through the rear panel.

Thank you very much for your help!!