Regarding PET/PER pin definitions for PXIe chassis

[TIFR]

Sir,
   I have some queries related to NI PXIe 1082/1075 chassis back plane. I am
developing my own custom PXIe 4 lane card/module which will be inserted into NI
chassis. I have some queries related to PXIe connector (backplane connector XP3):
1. As per PCI Express standard , I have routed PET signals from XP3 connector
to PER signals of my custom ASIC and PER signals of XP3 connector to PET
signals pf my custom ASIC. Whether this connection is correct? My device is
not recognised by the system (Using NI 8130 controller).Are their any BIOS issues for recogniziing custom boards in NI PXIe chassis? In case of NI chassis, whether PET should be connected to PET (and PER to ASIC PER) of my PCI Express ASIC?

2. Secondly PETn/p and PERn/p lanes also are swapped in 3 2 1 0 fashion
(instead of 0 1 2 4). Is it OK to swap lane for  both PER and PET signals.

3. Again I have inverted lanes for both PET and PER signals for routing simplicity Is it OK?

Kindly answer these question s urgently as my project is on hold.
regds,

Sunil G Kulkarni,
SO/F,Pelletron-Linac Facility, TIFR. Mumbai
PHONE:0091-22-22782291.

(M) 09323620467

India.

[Robert__R]

Sunil,

1.  The naming convention can be tricky if you don't know the reference point for PER and PET signals, so I'll use pin numbers.  XJ2 pins C5 and D5 should be connected directly to your ASIC's Rx (receive) lines.  Pins A5 and B5 should be connected through 0.1uF caps to your ASIC's Tx lines.  RefClk pins E4 and F4 should go through caps to your ASIC's RefClk pins.  If your ASIC doesn't terminate and bias the lines, you'll need to include termination and bias.

There aren't any BIOS issues for recognizing custom boards.  They should show up in Windows device manager, assuming you have a driver loaded.  There are driver requirements to get them to show up in Measurement & Automation Explorer in the right slot, but I'm not too familiar with that part.

2.  Lane reversal is an optional feature for PCIe.  If the downstream device (your ASIC) supports it there should be no problem.  If it doesn't, then the upstream device needs to support it.  Most NI chassis do, but I don't know that it's guaranteed.  I'm pretty sure the 2 chassis you mentioned support it, though I'm not sure if the 1075 supports it in all slots.  If you swap PER lines you must also swap PET lines, so they both need to be 3 2 1 0 or 0 1 2 3.

3.  There are no problems with lane inversion.

Good luck.

- Robert