Run IP Core on CLIP node at 50MHz?

[reevem]

We would like to target an IP core that runs at a base frequency of 50MHz onto a LabVIEW FPGA card via a CLIP node.  My experiments to date suggest this isn't possible.
 
LabVIEW does allow you to create an FPGA derived clock of 50MHz & to tie the CLIP node to that clock.  However "the compile process reported a timing violation" -- i.e. compilation failed.  Similar experiments with IP cores with clocks of 30MHz and 200MHz resulted in the same compilation error.

We would prefer not to alter the IP core (i.e. keep it at 50MHz), mainly for reasons of test comparison.  Does anyone have any suggestions?

Thanks.

* LabVIEW 8.6
* NI-PXI-8105 controller
* NI-7833R FPGA card

[RyanB]

It is definitely possible to compile a CLIP node to meet timing at 50 MHz.  LabVIEW FPGA has very little impact on whether CLIP logic will meet timing, are you sure that the IP core alone can meet timing at 50 MHz? 

Can you share the failing timing path or any details on the CLIP?

-RB

[reevem]

RB,

Thanks for your reply.  I have analysed the timing of the CLIP logic for 50MHz, and I can see that there are no failing paths in the IP core (I have run a separate timing analysis).  The timing violation does not occur until the Labview FPGA compile (interestingly, for both 30MHz and 50MHz derived clocks, but not 40MHz top-level).

I have changed tack a bit, and am experimenting with enclosing the CLIP call within a timed loop.  I will report back ASAP.