How can we adjust the Bandwidth of the Signal acquired using 5761R?
The Sampling rate is mentioned as 250 MS/s (Internal) and External to be between 175 MHz & 250 MHz.
As i understand, we have to keep a Bandpass Filter on the FPGA thorugh which we should be able to achieve this.
If we use the internal sample clock, we are achieving 50 MHz BW with 4 times DDC.
If we have to change the Bandwidth, what is the clock source to be used?
