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Regarding passing values between two targets

BMac,

in reference to your comment "..If you decide you want to go with FPGA-to-FPGA communication for low latency reasons, let me know and I can share some example code for serial UART communication with packet decoding. ..."

could you provide me with the example codes please?

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Message 11 of 17
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Could you provide a working example for serial UART for the FPGA-to-FPGA communication please.

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Message 12 of 17
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You bet. I'm cleaning up some code and testing. Assuming things go well I should be able to share it tomorrow.

Regards,

Brian

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Message 13 of 17
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Status update: This has taken longer than expected because of competing projects. But I am wrapping things up now on the serial interface code and expect to have it ready to share tomorrow. Thanks for your patience and sorry for the incorrect post on when it would be available.

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Message 14 of 17
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An updated version of the GPIC Reference Design application with support for the new AgileStack Power Converter Evaluation Kit is available below. To increase the reliability and reduce operating costs, the new AgileStack power converters are truly digital power converters that provide extensive built-in monitoring and diagnostic capability along with highly configurable fault detection, management, and recording. This combines with the extensive digital signal processing and advanced control capabilities of the NI General Purpose Inverter Controller, which provides a heterogeneous FPGA control platform with 58 embedded DSP cores and high level graphical programing tools with fully integrated model based design and power converter global optimization tools, including real-time power electronics simulation capabilities.

This example code includes the 5 Mbps serial UART interface to the AgileStack with FPGA based decoding of the serial packets containing the 3 phase currents, 3 half-bridge temperatures, and the DC link voltage. The GPIC analog inputs provide 3-phase grid and phase voltage sensing. The code includes the complete FPGA, RT, and Windows desktop user interface applications for the DC2AC converter, although automatic fault capture/logging is not currently implemented.

To extract, you must use 7-Zip or Winzip (not Windows built in ZIP archive utility) and you must unzip to a very short path such as "C:\PowerDev\" (not to your desktop):

ftp://ftp.ni.com/evaluation/powerdev/training/GPICReferenceDesign2014AgileStack.zip

A screenshot of the GPIC Serial UART Interface and Pack Decoder Logic is shown below, from "[FPGA] GPIC AgileSwitch 3-Phase DC-to-AC Inverter Control.vi".

GPIC Serial UART Interface and Pack Decoder Logic.png

See also the simple control and serial interface example under the FPGA UART folder, named "[FPGA] GPIC AgileStack Control.vi".

Notes:

  • In all of the examples, FPGA-based fault capture will be moved to the real-time processor application (using the DMA data stream) to free up a significant amount of FPGA resources. In the AgileStack DC2AC converter application, the real-time processor based fault capture feature has not yet been implemented. (In the SKiiP3/Methode SmartPowerStack examples, the FPGA-based fault capture implementation remains unchanged.)
  • An AgileStack example for DC2DC converter has not yet been implemented.
  • You will need to first update the AgileStack firmware and then reboot it (unpower, repower) per instructions from AgileSwitch. This is located on the website at: www.agileswitch.com/download.page
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Message 15 of 17
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Is there a simpler example for UART that I could work with, like a standard UART interface for baud rates of say 9600bps?

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Message 16 of 17
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If you are familiar with VHDL, there is a very simple fixed function IP core available from OpenCores. However, it does not have the same features and configurability.

http://opencores.org/project,uart

Here are application notes on how to integrate the VHDL into LabVIEW FPGA using the IP Integration Node.

Importing External IP Into LabVIEW FPGA

Using the IP Integration Node (FPGA Module)

http://zone.ni.com/reference/en-XX/help/371599K-01/lvfpgaconcepts/ipin_use/

Preparing IP for Use with the IP Integration Node (FPGA Module)

http://zone.ni.com/reference/en-XX/help/371599K-01/lvfpgaconcepts/ipin_prepare_ip/

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Message 17 of 17
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