5660 accuracy for hopping signal

[Rashid931]

Thanks a lot Chris.

As advised by you, I have created RTSI_Ref_Clk by selecting the radial button to compile for single frequency  and specify to compile it for 80MHz. But when I compiled the FPGA VI, I got the following error:

"PAR done!
 ERROR:Xflow - Program par returned error code 31. Aborting flow execution... "

Kindly guide me How can I remove this error so that my FPGA VI can be compiled successfully?

I have also attached the Xilinx log Report.

Device Utilization
---------------------------
Total Slices: 100.0% (13694 out of 13696)
Flip Flops: 51.5% (14096 out of 27392)
Total LUTs: 89.2% (24429 out of 27392)
Block RAMs: 64.0% (87 out of 136)

Timing
---------------------------
MiteClk (Used by non-diagram components): 33.28 MHz (138.06 MHz maximum)
RTSI_Ref_Clk: 80.01 MHz (69.74 MHz maximum)
Configuration_Clk: 20.00 MHz (179.73 MHz maximum)
ADC_0_Port_A_Clk: 25.00 MHz (191.24 MHz maximum)

[Chris_W.]

Hi Rashid,

That is my mistake, I forgot a couple of other differences between the 5640R and 5641R. The FPGA on the 5640R is about 1/3 the size as the one on the 5640R, so this application being as large as it is, seems to consume all available logic on the 5640R FPGA.

What I would do is actually change the compilation frequency for the RTSI_Ref_Clk to 50MHz, instead of 80MHz, as we can see from the compilation report that the max compilable frequency for that clock is actually ~67MHz. Sorry for that suggestion, my mistake.

The other thing that I would try is to change the Xilinx compile options to try to optimize the compilation more for space on the FPGA. You can do this by right clicking your 5640R resource and opening the Properties for that device. From the properties window, make the selections in the following image.

The other thing I would like to say is I'm sorry this is not a simple process, but this example was written specifically for the 5641R, which as you can see present some slight translation issues to the 5640R. However, since your application of a simple peak search/frequency hopping benchmark should actually end up being much simpler than the code here, when you can see how this works and you start to make the appropriate changes for your application, the device utilization should go way down and not be such an issue. Good luck.

Chris

[Rashid931]

Thanks Chris,

I spend an hour to compile FPGA VI and at the end, I get message "The compilation is failed."

How I can run FPGA VI in Emulation mode in Labview 2009 so that I can run FPGA VI before compiling it?

Thanks and Regards,

Rashid

[adnan_fazil]

Hi,

   I have installed LV2009. i have started working with labview FPGA with ni5640r as advised by you in one of your previous posts that a good starting point would be to take a look at the example program called ni5640R Analog Input, which is a basic analog input example.

I have tried this example. Now i am facing some problems. I have placed two subVI's ("scaled window" and "FFT") inside my FPGA VI. I have succesfully compiled the FPGA vi and recieving data from FPGA to HOST in my HOST VI.

Now i want to use the subvi i.e. "FFT to Spectrum" to dispaly the spectrum on Front panel but the problem is that i m recieving binary data from FPGA to HOST and i dont know that how can i plot this data in form of a power spectrum either  by using "FFT to spectrum.vi" or any other method.

I m attaching the complete project with the post so that u can understand my problem easily.

Waiting for ur valueable comments and suggestions.

THANKS IN ADVANCE

BEST REGARDS

ADNAN FAZIL

[adnan_fazil]

Sorry here is the attachment.

[Chris_W.]

Hi Adnan,

I think the simplest way to get the data into the correct form (Power (Vrms^2)), would be to use a method similar to the way it is done on the example VI that I linked way back.

Basically what you need to do is square the magnitudes of the I and Q (real & imag) data that is returned from the FFT on the FPGA VI, and add them together.

And pass this on to the Host VI. On the host we can then finish the calculations. First, you would need to take the square root of the data being returned, then you can split the data in the middle of your FFT array and re-order it. Then you would need to take that data and take the Log(10) of it and multiply by 20, to get it be properly scaled into dB. You should also then subtract the downconverter gain you get from the 5600 properties. Here's what it looks like:

I went ahead and made these changes to your code and re-attached the project. Give this a try.

Also, I was curious, what was the issue you were having trying to use the FFT to Spectrum.vi? Was it not returning the proper data? you should have been able to simply split the I and Q FFT data and pass it in and receive the power spectrum data out, which should have been usable feeding it straight into a waveform graph.

The other thing to keep in mind is that for your application, you really don't need to do most of these things for presentation, since all you're concerned about is to find the peak in the data and return the frequency at which it is. So, you should really only need to find the magnitude of the I/Q resultant vector and returning just its frequency value all on the FPGA.

Chris

[adnan_fazil]

Thanku so much Chris, for giving your valueable time.

I have tried the project that u have sent to me in the last post.The problem is same that the graph doesn't show any useful information even when genrator is active. After testing the project i have made some changes in tha host vi and i need your feedback for that changes (but these changes dont make any diffrence to the spectrum graph). I m attaching the image of the changes for ur quick reference. i m also attaching the project (with edited host vi) and the generator vi for PXI-5652.

The problem is same for both options in the host vi. The graph dosen't show any change even when my PXI-5652 is running in the specified frequency band i.e. 220-240Mhz. When i start my generator vi, the graph shows some distortion but dosen't give any useful info like some peaks or any major change.

I am attaching both the project and the generator vi so that u can try this yourself .

Waiting for your response.

Once again THANKS for ur valueable time and efforts.

REGARDS

ADNAN FAZIL.

[Rashid931]

Hi Chris,

You look quite busy now a days. But I am really grateful to you for your informative ideas which you shared with me and Mr. Adnan. I want to request one thing that I feel that Mr Adnan's problem is still not resolved because I have also tested the code which you posted in your last post named "Adnan_edit". I found that the host VI is still not giving any meaningful data. I request that If you kindly run the code in actual Hardware scenerio, then you can observe the problems in real time and you can edit the code on the spot. I hope Mr. Adnan is really in need of your kind and generous guidance. I also learn a lot from your replies to Mr. Adnan.

Waiting an early generous reply from your side.

Thanks in advance,

Rashid

[adnan_fazil]

My dear Chris,

                  Are you angry with me?  .Its a long time that i didn't hear any guidance from your side. My project completion date is approaching but i am unable to run my host vi. I have already posted my editted vi's for your advice. I am very greatful to you that you always helped me alot. I am sure that you are the only one who can take me out of this problem.

                 Hoping to see an early response from your side. Thanks alot in advance.   

BEST REGARDS

Yours truely

Adnan Fazil

[Rashid931]

Hi Chris,

         Thanks a lot for your guidance. I have written a small Project for PCI-5640R and PXI-5600 . But unfortunately, I am unable to see the meaningful FFT.  I have attached my Project with this e-mail. Kindly guide me that what is the mistake in my code.

Thanks and Regards,

Rashid