Continuous/long acquisition...or streaming to memory for the PXI-5660

[cochenob]

I am looking to do continuous FSK acquisition on the PXI-5660.

After some study...it appears that the PXI-5660 cannot "stream" the full 20MHz BW back to the controller due to the 133MHz bus speed.  My second option was to just do a "single shot" acquisition...but just set the acquisition time to be really long to make sure I got all of my data.  However...I've also learned that the onboard memory in the digitizer will only record about a half a second or so of data. 

I've seen that if I set the BW to <1.25MHz...then I CAN "stream" data back "real time" since the digitizer rate gets dropped significantly.  There's an FM software radio example floating around here that seems to be able to do this.  

Two questions off the bat....1)Is this reduction in sampling rate automatic for all the VI's?  Is there a VI in particular that does this?  Are there ones that don't?  2)If I decided to still do "one-shot" type acquisition and store data on the onboard digitizer memory, I should be able to extend that half a second or so to a few seconds, right?

My second idea...is there any way to "stream" digitizer samples to memory somewhere that doesn't involve shipping it back over the bus back to the controller?  It seems like I'm pretty much at the mercy of the bus bandwidth here.  Is this accurate?  Said quite simply...is there any way to capture longer amounts of data (or equivilently more BW) and process it later without having to either store it in A/D memory or ship it to the controller over the PCI bus?  Is 1.25MHz the best I can hope for for the PXI-5660?

Thanks for the thoughts.

---

BC

[cochenob]

A follow-up question...

Is it possible to use the on-board digitizer memory sort of like a "buffer"?  In other words...can I set things up so that the digitizer is streaming data out over the bus to the controller while it is simultaneously being filled up with new samples?  This may be a work around to providing continuous acquisition...

[Andy_Hinde]

Hello BC,

I will try and address your questions below:

Two questions off the bat....1)Is this reduction in sampling rate automatic for all the VI's?  Is there a VI in particular that does this?  Are there ones that don't?  2)If I decided to still do "one-shot" type acquisition and store data on the onboard digitizer memory, I should be able to extend that half a second or so to a few seconds, right?

You are correct - the PXI-5660 samples @ 64 MSPS whenever the configured bandwidth is > 1.25 MHz, and the PXI-5660 samples at 2 MSPS starting at bandwidths < 1.25 MHz, with the sampling rate dropping in increments as the bandwidth is reduced below 1.25 MHz. The onboard Digital Downconverter (DDC) turns on at configured bandwidths of < 1.25 MHz.

The reduction in sampling rate is automatic when using the normal software interface for the PXI-5660 - the ni5660 VIs.

This includes specifically the ni5660 Configure for IQ.vi and the ni5660 Configure for Spectrum.vi. In your uase case, you would be acquiring IQ data and would use the ni5660 Configure for IQ.vi. Please see the ni5660 shipping examples installed by the NI-RFSA driver.

Programming the PXI-5660 via the NI-Scope/NI-Tuner drivers separately, as opposed to using the NI-provided integrated ni5660 API, will not provide the behavior described above. The DDC will not be configured and turned on, and as a user you do not want to be trying to program the DDC directly through NI-Scope property nodes.

The ni5660 Configure for IQ/Spectrum VIs have internal subVIs which enable and program the onboard DDC to preset configurations.

Were you to perform a one-shot IQ data acquisition, storing as much data as possible into onboard digitizer memory, the max time duration you can capture will depend on your PXI-5620 digitizer's memory option and the sampling rate configured.

With the DDC (i.e. bandwidth > 1.25 MHz) you are sampling at 64 MSPS with each sample being real and 2 bytes wide. This means you are capturing 128 MB/sec of data. If you have the 32 MB memory option, you can capture 250 ms of data. The 64 MB memory option gives you 500 ms of capture time.

If the DDC is on with the BW is set to 1 MHz, the sampling rate is set at 2 MSPS with each sample complex and 4 bytes wide. This means you are capturing 8 MB/sec of data. The 32 MB memory option would provide 4 seconds of data capture time, and the 64 MB option would provide 8 seconds of data capture time.

My second idea...is there any way to "stream" digitizer samples to memory somewhere that doesn't involve shipping it back over the bus back to the controller?  It seems like I'm pretty much at the mercy of the bus bandwidth here.  Is this accurate?  Said quite simply...is there any way to capture longer amounts of data (or equivilently more BW) and process it later without having to either store it in A/D memory or ship it to the controller over the PCI bus?  Is 1.25MHz the best I can hope for for the PXI-5660?

Transferring the data from digitizer memory would require the data to be srtored somewhere - either RAM or disk. Both require DMA which passes through controller RAM anyway. There's no secret workaround for what is described above. If you capture bandwidth larger than 1.25 MHz, you will need to acquire single-shot data to onboard digitizer memory. If you reduce the captured BW below 1.25 MHz, the DDC turns on and you now have data streaming as an option.

Is it possible to use the on-board digitizer memory sort of like a "buffer"?  In other words...can I set things up so that the digitizer is streaming data out over the bus to the controller while it is simultaneously being filled up with new samples?  This may be a work around to providing continuous acquisition.

What you describe in the paragraph above is continuous acquisition - a circular buffer being emptied and filled from opposing ends with the emptying process required to be faster than the fill process (to prevent buffer overflow). Again this is only possible with the PXI-5660 DDC enabled, with configured bandwidths < 1.25 MHz.

Regards,

Andy Hinde

RF Systems Engineer

National Instruments

[Andy_Hinde]

Hi BC,

I'm attaching example code for streaming PXI-5660 to HDD and reading it back from file.

Regards,

Andy Hinde

RF Systems Engineer

National Instruments

[cochenob]

Thanks Andy-

This is pretty much what I expected.  Two quick follow-up questions...

1) It makes sense that when the sample rate is reduced (from 64MS/s to 2MS/s) that the resolution can be increased (in this case, from 2Bytes to 4Bytes)....however 4 Bytes seems like a lot....as in something approaching 32-bits!  Are we really talking about that kind of resolution or is something else going on?

2) What is different about the A/D in the PXI-5661 that allows the full BW to be streamed?

Thanks again.

---

Brandon

[Andy_Hinde]

Hi Brandon,

1) It makes sense that when the sample rate is reduced (from 64MS/s to 2MS/s) that the resolution can be increased (in this case, from 2Bytes to 4Bytes)....however 4 Bytes seems like a lot....as in something approaching 32-bits!  Are we really talking about that kind of resolution or is something else going on?

When the DDC is enabled, it produces two 16-bit words for each complex sample - 16 bits for I and 16 bits for Q. Each complex sample is comprised of a two byte word for I and for Q.

2) What is different about the A/D in the PXI-5661 that allows the full BW to be streamed?

The PXI-5661 uses a different digitizer module, the PXI-5142. The PXI-5142 has a wider bandwidth DDC (20 MHz max) which allows the DDC to always be on. This is also the case with the PXIe-5663 and PXIe-5663E, which use a PXIe-5622 digitizer that has a 50 MHz max BW DDC. The difference is the DDCs that are present on the digitizers.

Regards,

Andy hinde

RF Systems Engineer

National Instruments

[cochenob]

Perhpas you can explain what exactly the function of the DDC is in this case.  I assume it's downconverting to baseband...but you still have a 20-50MHz BW which is still too big to stream back to the controller.  20MHz of BW is 20MHz of BW whether it's been downconverted or not...I seem to not be considering something.

---

Brandon

[Andy_Hinde]

Hi Brandon,

The DDC downconverts, filters, and decimates the IF data to complex IQ data with a lower sample rate. The 5660 acquiring 20 MHz BW samples at 64 MSPS acquiring real data (DDC off), for a data rate of 128 MB/sec. This is too close to the PCI/PXI bus theoretical max.

The 5661 acquiring 20 MHz BW samples at a rate of 25 MSPS acquiring complex IQ data, for a data rate of 100 MB/sec. This is far enough below the PCI/PXI bus max to be sustainable. In this case, you would still not be able to stream it to an embedded controller hard drive, since a single laptop-sized HDD doesn't have the write speed needed to keep up with this. You could, however, easily stream 100 MB/sec to a RAID0 array of disks, using the NI 8260, 8264, and 8265 for example.

The 5663/5663E acquiring 50 MHz BW samples at a rate of 62.5 MSPS acquiring complex IQ data, for a data rate of 250 MB/sec. This is well below the PCI Express/PXI Express x4 bus speed of 1 GB/sec and is easily sustainable. You still cannot stream this to an embedded controller hard drive, but you could stream this to a 8264/8265 RAID0 array.

Here is a link to NI's Developer Zone on an Introduction to RF Record and Playback:

http://zone.ni.com/devzone/cda/tut/p/id/7209

Regards,

Andy Hinde

RF System Engineer

National Instruments

[cochenob]

"The 5661 acquiring 20 MHz BW samples at a rate of 25 MSPS acquiring complex IQ data, for a data rate of 100 MB/sec."

Sounds like the trick is a careful scheme of undersampling then?

[Andy_Hinde]

Hi Brandon,

It may seem like undersampling, but this is not the case. The difference is we're working with cimplex data, not real data.

We'll continue using the 5661 as an example.

The 5661 uses the 5142 digitizer, which has a DDC which is always on. The 5142 ADC (before DDC in signal chain) runs (always) at a sample rate of 100 MSPS, acquiring real IF samples with the analog input signal centered around 15 MHz. The 100 MSPS ADC samples (real, IF data) are fed into the DDC.

The first thing the DDC does is downconvert the real, digital IF samples from IF (15 MHz) to 0 Hz (baseband). You're 20 MHz signal (sampled IF signal is always 20 MHz due to the 5600 analog bandwidth - filtering occurrs afterwards in the DDC) is centered at the IF frequency, after this digital downconversion the signal is centered at 0 Hz, from -10 MHz to +10 MHz.

Next, the DDC applies digital filtering to reduce the signal bandwidth to the requested value. In this case we'll continue with assuming we're acquiring 20 MHz BW. In this case the signal remains 20 MHz wide.

The final stage is the decimation (sample rate reduction) step. Here we lower the data rate from 100 MSPS to something smaller (this is why filtering is done before decimation - to prevent aliasing). Since the data is complex, it is centered at 0 Hz. For 20 MHz complex data centered at 0 Hz, the signal spans -10 to +10 MHz. A 25 MSPS complex sample rate is more than twice the max signal frequency of +10 MHz.

Regards,

Andy Hinde

RF Systems Engineer

National Instruments