How to lock sampling frequency for 5673 and 5663

[Clayton_A]

Hello,

In general I'm trying to lock transmitter and receiver together.  It seems easy to lock the carrier frequency, however no matter what I do, I seem to have a drift in my sampling frequency (on the order of 1ppm).

Is the sampling clock in the 5663 digitizer tied to the same clock reference as the LO?  ... I didn't think I would need the TClk mechanism here since I don't care about delay ...

Any thoughts are greatly apreciated.  Below are a few specifics.

I'm using the 5673 as transitter and 5663 as receiver.  I've noticed the folowing:
1. When each are using a 'Reference Clock Source' = OnboardClock I have a noticeable carrier offset at the receiver (eg 5.8 GHz carrier has  ~7 KHz offset) and this is fine.
2. When each are using a 'Reference Clock Source' = PXI Clock, with the chassis physically tied, I see no noticeable carrier offset at the receiver.
3. When 5673 is using 'Reference Clock Source' = OnboardClock, 5663 using 'Reference Clock Source' = ClkIn (ClkIn/Out physically tied), I see no noticeable carrier offset at the receiver.

[Travis_Ann_N]

Hi Clayton,

After looking into your question a bit, I saw that you were able to get some assistance with one of our other Applications Engineers. For the sake of the forum, I just wanted to follow up with a summary. In the case of your particular issue, you can continue working with the Applications Engineer with your service request. 

The sync your VSG and VSA, you can export the reference clock on the VSG and use it as the Ref In for the VSA. In this particular situation, the use of a splitter was recommended based on the version of his NI 5652, which only has 1 Ref In/Out port. 

Regards,

Travis Ann

[Clayton_A]

I am confused about the digitizer reference clock, I'm not really sure how it works. There is a property called "digitizer sample clock time base source," however I can't seem to set this to ClkIn. I get an error when I try. When I poll the "digitizer sample clock time base source" property, it always shows OnboardClock regardless of my configuration. Is the LO generating a 150 MHz clock for the digitizer by default? The default configuration has the LO ref_In/Out wired to the Clk_In on the digitizer. If this LO reference to the digitizer is disconnected what happens, does it then use the PXI or an internal clock?

[Travis_Ann_N]

Hi Clayton, 

The digitizer sample clock time base source is different from the Reference Clock source. I've copied  a description below of the difference between the two from the digitizers help. 

Clocking:Reference (Input) Clock Source:

Specifies the input source for the PLL reference clock.

Clocking: Sample Clock Timebase Source:

Specifies the source of the sample clock timebase, which is the timebase used to control waveform sampling.

Yes, the default configuration of the NI 5663 is for the NI 5652 to export its internal 10 MHz reference to the NI 5622 so that the NI 5622 and the NI 5652 devices are frequency-locked. The NI 5663 can also be configured to lock to an external (10MHz only) reference source. The NI 5663 can also be configured to lock to the PXI 10 MHz backplane clock. Locking to the PXI 10 MHz reference does not require a cable, but this configuration does not provide the same frequency and phase noise performance as the NI 5652 internal Reference clock. All of this information is provided in detail in the NI RF VSA Help. See the directory below:

Regards,

Travis Ann

[Clayton_A]

Thanks Travis. 

My biggest concern was that the LO and digitizer weren't actually being tied to the same clock. I'm seeing a slight frequency offset at the receiver. While I originally thought it was a ~1-2ppm sample frequency offset, now I suspect it's a less than 20 ppb carrier offset.  I've stopped trying to characterize the offset, but does that number make sense when syncing 5663 to the 5673 clock out? 

[Clayton_A]

After a bit more analysis, I'm definitely seeing a clock offset between the 2 devices.  It's small, but it's visible. Here is a typical example (white I, red Q).  Both RX and TX are tuned to 3.65GHz, TX is playing a carrier only, while RX is sampling at 1MHz and captures 8M samples, notice that we see 2 cycles in 8 seconds.  So there is roughly .25 Hz offset in this case.

 This might sounds negligible, but it's significant in our testing. 

[Travis_Ann_N]

Hi Clayton,

How are you coding this in LabVIEW? Have you taken a look at the RFSA Synchronization with TClk and RFSG.vi example in the RFSA Shipping Examples? It uses NI-TClk to make the NI-RFSA and NI-RFSG start at the same time.

Travis Ann

[Clayton_A]

Hey Travis,

I'm not concerned with delay.  It's the frequency offset that I don't want. 

[Andy_Hinde]

Hello Clayton_A,

What you describe below with regards to your three scenarios of reference clock sources is expected behavior.

A signal generator is tuned to some carrier frequency based on its LO frequency(s), and the LOs are synthesized rrom PLLs using a ref clock. Same for a signal analyzer. So, each instrument will have its own idea of what 1 GHz is, for example, if they are using their own, independent onboard reference clocks. This is why you get a frequency offset between Tx and Rx.

Locking the instruments to a common reference clock removes the frequency offset, as you have observed. This common ref clock can be exported from one instrument and imported to the other, or imported to both instruments from an external source (like the PXI backplane).

The ADC of the analyzer and DACs of the generator don't have to be synchronized to remove the frequency offset, I'm going to read the following posts to try and understand your issue better.

Regards,

Andy Hinde

RF Systems Engineer

National Instruments

[Andy_Hinde]

Hi Clayton_A,

"I am confused about the digitizer reference clock, I'm not really sure how it works. There is a property called "digitizer sample clock time base source," however I can't seem to set this to ClkIn. I get an error when I try. When I poll the "digitizer sample clock time base source" property, it always shows OnboardClock regardless of my configuration. Is the LO generating a 150 MHz clock for the digitizer by default? The default configuration has the LO ref_In/Out wired to the Clk_In on the digitizer. If this LO reference to the digitizer is disconnected what happens, does it then use the PXI or an internal clock?"

The digitizer reference clock is the ref clock that the digitizer uses to synthesize the 150 MHz sample clock. The LO is not involved in any way with the digitizer sample clock, aside from the fact that they are synthesized from the same reference clock. The default configuration is for the 5663 to use its onboard ref clock, so the 5652 module synthesizes the LO from the 10 MHz clock present on the 5652 module, while at the same time exporting this 10 MHz to CLKIN of the 5622 module, which imports it and synthesizes the 150 MHz sample clock. If you were to choose the PXI backplane as the ref clock source, the 5652 and the 5622 would both import the 10 MHz from the backplane and you could actually remove the cable between the 5652 and 5622 with no ill effects.

If you set the 5663 ref clock source to PXI backplane and remove the cable, you will see nothing happen. If you have the 5663 ref clock source set to onboard clock and remove the cable, you will receive an NI-RFSA driver error telling you that the digitizer has lost PLL lock.

Regards,

Andy Hinde

RF Systems Engineer

National Instruments