niRFSG write arb waveform error

[margarette]

Hello, I'm trying to transmit an RF Signal. I'm using the NI PXIe-5611 as the resource. But when I run the program, an error shows in the front panel. It says that the PLL could not phase-lock to the external reference clock. I attached the screen shot of the error. What is the source of the error and how can I solve it? I also attached the picture of the connection of the modules. Thank you.

[Jake_G]

Hey Margarette,

Does the Active light on the 5450 turn red at any point?

If so, it may be because the VCXO on the PXIe-5450 is not properly able to lock phase to the reference clock with the on board Phase Locked Loop (PLL) circuitry. Resetting the device may temporarily remedy the problem, but it is likely that the device will have to be sent back for RMA.

If the light does not become red, it may be that because the driver may falsely report that the PLL successfully locked to the reference clock. This happens specifically when the time is short between a Commit with the new clock source and a Wait Until Settled is called. A commit can occur either through the Commit VI or when writing a waveform. Wait Until Settled is called through the VI of the same name and Initiate. As a workaround, you can add a wait in between the Commit and Wait Until Settled. Ideally, with a 500 ms wait, the problem should not occur. With a shorter time the problem may become less frequent, but it is not guaranteed that the error will not occur.

I hope this helps, and good luck!

Regards,

Jake G

Applications Engineering

[Andy_Hinde]

Hello Margarette,

You need to move the blue, flexible SMA-SMA cable you have connected between 5450 CLK IN and 5652 RF IN/OUT to instead connect to 5652 REF OUT2. The error is being generated because the 5450 is expecting a 10 MHz signal at CLK IN that it isn't receiving.

This configuration leaves the REF IN/OUT terminal free in case you want to connect an external 10 MHz reference to the 5673 via the front panel.

Regards,

Andy Hinde

RF Systems Engineer

National Instruments

[margarette]

Hello Jake and Andy,

Yes, the active light in 5450 turns red. I haven't tried moving the SMA-SMA cable since I don't want to change the hardware connections in the chassis yet. I fear that I might damage it if I do some mistake. Anyway, when I run the NI RF Phase-Coherent Multi-channel signal generation, there are no errors. However, when I try my own code, the PLL error occurs. What could be the reason behind this? 😞

[Andy_Hinde]

Hello Margarette,

The NI RF Phase-Coherent Multi-channel generation software has default settings which onfigure each channel to import its reference clock from the PXI backplane. So, the PXIe-5652 LO module and each PXIe-5450 AWG module all import the ref clock from the backplane and do not make use of the front panel ref clock cables. 

You can also use the PXIe-5652 onboard reference clock as the master ref clock source by setting the clock source to Onboard. This will have the 5652 module lock to its onboard ref clock source and export it to the REF OUT2 terminal. It is then daisy-chained through the CLK IN/CLK OUT terminals of each 5450 AWG. The NI RF Phase-Coherent Multi-channel software demonstrates how to write the code to do this when the ref clock source is set to Onboard.

Here is a link to the Getting StartedWith the NI 6 GHz MIMO Platform document online:

http://www.ni.com/pdf/manuals/373158b.pdf

I'm also attaching a screenshot from this document showing the 5673E cable connections. This should give you confidence that changing around the front panel ref clock cables is safe and won't cause any damage to your system.

Regards,

Andy Hinde

RF Systems Engineer

National Instruments