Adding amplitude offset to sine generator on PCI 7830R

[panoramic]

Hi,

I'm trying to add a dc offset to the sine generator in this reference design: 

DDS Waveform Generation Reference Design for LabVIEW FPGA

I can pass the offset parameter into the FPGA vi but when it is passed into the sine generater sub.vi the response becomes very slow.  

If I try to add the offset to the sine generator sub.vi output (within the FPGA vi) the same thing happens.  The analog output steps its way up and down very slowly as if the FPGA is bogged down with a very long delay.

But the sine generator has a phase offset built in that works just fine.   All I need is an amplitude offset. 

Help is very much appreciated!

LG 

[Eli_S]

Hi LG,

What do you mean exactly by the amplitude offset parameter? The only parameters you have in the FPGA VI are phase shift, signal amplitude,accumulator increment, and update rate. I am not sure what you are refereing to as the amplitude offset.

Please clarify this.

Thanks!

[panoramic]

Hello Eli,

I'm trying to add a new parameter for the DC amplitude offset.  I do this by copying the signal amplitude parameter in the FPGA vi, pasting and then renaming the parameter Offset1.  

After compiling to generate the bitfile the Offset1 parameter is available to the Host VI but and the Offset works but the whole things runs very slow.

I'm not sure if I'm creating the new Offset parameter in the FPGA vi correctly?

LG 

[panoramic]

Hello Eli,

It turns out the real issue is adding a parameter to the FPGA VI.  If I attempt to add a new parameter for the DC offset and transfer it to the host vi the application bogs down.

If I use an exisiting parameter, eg. convert the Signal amplitude from CH2 into a DC offset for CH1, it all works.

So really my question is how do you add parameters to this sine generator reference design?

Thanks!

LG 

[Eli_S]

Hi LG,

I noticed that you are also working directly with Rob K. on this issue via email. We spent some time looking over this example, and there are a few questions we need clarification on. Rob has emailed you this directly, but I am going to state here again.

Where are you seeing the slow update rate? Is this the actual signal being output on the AO line of the board, or is this the host software that is going very slowly? If it is on the actual output, it is possible we are outputting the same values out over and over again, basically changing the frequency of the sine wave drastically. If it is on your host VI, then we should see why it is slowing down, possibly looking at the processor usage of the controller.
 
Secondly, I understand that you copied one of the values and now are writing to it from a read write control. This should work fine, but I am curious where you have implemented this into your FPGA VI. Keep in mind that the FPGA uses integer math, so a value of 1 is not 1V, but is calculated using range/2^bit, or 20/2^16
 
Also, since this reference example has several different exampled within it, can you tell me which VI's you are modifying?  It may be best to get screenshots of the components you have changed.

Thanks!

Eli Seidner - NIC