Best Method to transfer Large Fixed Size Data between FPGA and Host on PCI-7830R?

[raa1964]

Hi, I am coming from hardware background and new to Labview FPGA. I have developed a design in VHDL and I want to implement it on PCI-7830R. the design takes a grayscale image and apply some filtering to it using parallel techniques. I was able to follow the steps and succeeded in inserting the VHDL code in LabView.

My problem is in how to communicate the large data (pixel values in the image) from host to FPGA and the other way. The size of data is known and fixed.  I read the different methods in the help and looked at some examples. I figured out that probably the best solution is to use a DMA FIFO. In my VHDL code at the FPGA side, each data element in the FIFO is supposed to be distributed to a different 12-bit register defined in my VHDL. My question is: can I distribute the data, one element per register  each cycle of the 40 MHZ without missing any data element?. For example, say I have 16 12-bit registers. I am supposed to put 16 12-bit elements in the FIFO. Then every clock cycle one element will go to a specified register in the FPGA; thus load all 16 registers in 16 cycles. If possible how can I do such synchronization? If not, what is the best method to guarantee not to miss any data element?

I really appreciate any help in this direction.

Regards

[DavidVr · Accepted solution]

Dear raa1964,

  On FPGA side you are able to insert elements into the FIFO only one-by-one. The best is to use for example a single cycle timed loop. On the host side you can chose to read the data in three modes:

• Blocking – Host DMA FIFO Read waits indefinitely to read a fixed number of elements from the FIFO
• Polling – Host DMA FIFO Read reads all of the available elements in the FIFO at a user-defined rate.
• Polling with a Fixed Number of Elements – Host DMA FIFO Read reads a fixed number of elements at a user-defined rate.

I've attached screenshot of these methods. Generally I like the polling method best, this way you make sure no data is missed. You may also find useful information on the following link:

http://zone.ni.com/devzone/cda/tut/p/id/4534

Hope I gave you enough information for the starting!

Best,

David Varga

[raa1964]

Thanks a lot DavidVr. I tried the different methods you described. I found the third method most convenient for my application. It took me a while to get it to work because I am still in the stage of getting familiar with LabView FPGA.