Hello,
I have 2 Compact Rio's. One contains six 9215 modules, the other contains six 9233 modules. In addition, each cRIO has another 9215 that i use as a trigger signal to both. Basically the FPGA code is such that i have an outer loop looking for the input trigger voltage to be above a certain threshold, and then i run the inner loop and dump data to the DMAFIFO. The issue i am having is that when a function generator signal is sent to both, i am getting approximately 160us delay between the two (the 9233 is always delayed). Once i realized our data looked skewed, i did some digging and found all Delta Sigma moudules have this delay. The manual represents this as "input delay" and has the following equation:
>25.65 kS/s ................................9.8/fs + 3 μs
So i calculate it as 9.8 / 50,000 (my sampling rate) and add three microseconds and come up with a delay of 199 microseconds. This is relatively close to what i am seeing with the signals (160 microseconds).
1. Is the formula correct as i see it?
2. Is this a "startup" delay because i only see it causing a shift in the data, meaning the signals are in sync, just one is delayed behind the other.
3. Is it worth trying to correct this in code by delaying the 9215 (which has no "input delay") or should i just delete 160 microseconds (8 samples) of data (which running at 50K is 20 microseconds per sample) from the 9233 modules in order to align the data?
4. Why, if this is a self timed loop (which is different from the 9215 loop in which i placed a loop timer) does this not account for this delay?
5. When exactly does this sample? I know it takes successive samples so that it can increase bit resolution but when does it actually transfer the data to the FPGA? Should i be worried about the "average" succesive samples not being representative of the sample that is returned?
I realized there may be betters ways to sync these cRIOs but this was my first cRIO/FPGA project and i do not have the time to start over. Thanks in advance.
