Can tdms streaming vi's be used in LabVIEW Realtime?

[preston_johnson]

Sorry for the confustion,

Depending on the backplane you have either 92kbyte or so or 192kbyte or so of FPGA memory for your DMA buffer.  Fortunately, you will need only 1kbyte for your 2 channel application.  This is the DMA block that you configure and access in FPGA. 

On the RT side, you will want to configure the DMA buffer to say 4M.  Once your read completes, use the scaling VIs in the LabVIEW/examples/compactRIO/shared folder to apply calibration constants and to scale to voltage.  You can then scale to engineering units. 

In the read loop, you have one loop that checks the amount of data in the DMA buffer and if it is not enough, you sleep for say 20ms.  Once there is enough, you terminate the wait loop, read the data from the DMA buffer, scale it, and write it into a QUEUE.

You have another loop that pulls data from the QUEUE and writes it to the TDMS files.  The QUEUE allows these two loops to operate in parallel and the QUEUE provides a FIFO buffer between the two loops - the producer which reads data from the DMA read, and the consumer which stores the data.  You can also use a RT FIFO instead of a QUEUE.

Hope this helps

[FWalker]

Appreciate your advice preston, and everyone else I will definitely consider everything you mentioned.   Could you also get me pointed in the right direction as far as being able to collect exactly 2sec of data every time, that would be exactly 200000 points of data saved to a .tdms file.    I don't mean the specifics on DMA and QUEUES but exactly how does settings such as block size and scan rate effect how much data I am trying to acquire?    I know that it is not 100% predictable due to overhead, memory management, and my skills as a programmeer but is there a general rule of thumb as far as frequency settings go?

[preston_johnson]

I think your scan rate is the key factor.  If you want 2 seconds of data and 100kSA/sec, you need to run your I/O module at 100kHz.  Move this data point by point into the DMA buffer on FPGA. 

Set your read DMA on the RT controller to read 400,000 points (2 points from each channel).  the read will now return two seconds of data. Since the data in the DMA buffer is 4bytes per point, you need 1.6MB DMA buffer size.  I would alloccate 3.2MB to give you some head room. 

[FWalker]

I am using the ni-9201 Analog input module.  I know its capable of 100kS/s but is this an adjustable setting or a property?  Just checking to make sure.

[preston_johnson]

The 9201 module is a polled module, you will need to put an I/O read node for the channels you want in a loop with a timer to clock the loop.

[sado]

My cRIO 9233 allows me 4 audio channels but i see there's only 3 DMA FIFO channels.  So i tried to double up my DMA channel and i get the error below.  It's there a way to overcome this problem?

Error:

At least one DMA channel is used by several FIFOs, which is not supported.

Configure FIFOs to use a unique DMA channel by specifying a different DMA Channel in the FIFO Property Page.

Thanx,

Sa

[Brian_R]

There are two possible optimizations you can do to send 4 channels across 3 possible FIFOs.  The first is to interleave data.  You can feed your seperate channels down 1 (or more) DMA FIFOs and use the Decimate 1D Array.vi on the host side to assemble the data properly. 

The other optimization is to consider the width of the FIFO.  They are 32 bits wide.  If you are sending data that can be represented in 16 bits, you can effectively send two channels on one FIFO.  If you can represent your data in 8 bits, you can send all your data in one FIFO. 

These are my best suggestions to implement your task.

[Bassett_Hound]

Sa,

Its most likely that you've configured two or more of the FIFOs to use the same DMA channel.  You'll have to configure them to use separate channels.

Regards,

Bassett

Message Edited by Bassett Hound on 09-21-2007 10:44 AM

[StevenA]

Hey Bassett,

I'm interested in the DMA method you mentioned in one of your posts...

>Each DMA transaction has overhead, so reading larger blocks of data is typically better. The DMA FIFO.Read function automatically waits until the Number of >Elements you requested becomes available, minimizing the processor usage. However, cpu usage may increase if the data is coming in at a slower rate.  This is >because the heuristics used in the DMA API to determine when to sleep or to poll depend on the amount of data and number of elements still coming.  If its small it >might still spin and drive up the cpu usage.  Its better to use some mechanism to ensure data \space is available, rather than relying on the blocking behavior on the >host DMA nodes.  I manage this by using interrupts, timed loops, polling by reading 0 elements, or scheduling followed by polling.

Can you point me to an example that uses interrupts as you described here?

Steve

[Eli_S]

Hi Steve,

You can find examples on interrupt and polling synchronization in the LabVIEW example finder. To get to these examples go to the help menu in LabVIEW and click on "Find Examples..." Once in the example finder, go to Hardware Input and Output » CompactRIO (or R-Series) » FPGA Fundamentals » Host Synchronization