CompactRIO Deploy Error "LabVIEW: Resource Not Found."

[Nullified]

Hi,

I am using a CompactRIO 9002 and LabVIEW 8.5.  I made a simple FPGA VI to read out a bunch of analog inputs and write out a square wave to some analog outputs.  Then I made another VI to run on the Real-Time Target to convert the scaled frequency and scaled duty cycle inputs to actual duty cycle and frequency values.  When I try to deploy the Real-Time VI, I get the following: 

Deploying r03fsae  (successfully deployed target settings)
Deploying Check Special Tags.vi  (5.89 K)
Deploying GetRTHostConnectedProp.vi  (3.41 K)
Deploying Search and Replace Pattern.vi  (8.11 K)
Deploying nirviFillInErrorInfo.vi  (8.09 K)
Deploying niLvFpgaErrorClusterFromErrorCode.vi  (11.27 K)
Deploying nirviErrorClusterFromErrorCode.vi  (5.93 K)
Deploying Error Code Database.vi  (3.67 K)
Deploying Find Tag.vi  (10.43 K)
Deploying Merge Errors.vi  (6.75 K)
Deploying Trim Whitespace.vi  (3.71 K)
Deploying nirio_MultilineStringToArray.vi  (8.81 K)
Deploying nirio_AppVersionToI32.vi  (3.96 K)
Deploying Error Cluster From Error Code.vi  (23.42 K)
Deploying _nirio_device_attrSetString.vi  (9.46 K)
Deploying _nirio_device_close.vi  (9.90 K)
Deploying nirio_Read32.vi  (13.07 K)
Deploying _nirio_device_open.vi  (11.59 K)
Deploying nirio_Write32.vi  (13.01 K)
Deploying _nirio_device_writeBlock8.vi  (9.83 K)
Deploying nirio_Write8.vi  (13.01 K)
Deploying _nirio_device_configSet.vi  (11.42 K)
Deploying nirio_DMAReconfigureDriver.vi  (16.63 K)
Deploying _nirio_device_writeBlock32.vi  (9.36 K)
Deploying nirio_Read8.vi  (13.04 K)
Deploying nirio_DMAStopAll.vi  (11.39 K)
Deploying _nirio_device_attrGetString.vi  (13.06 K)
Deploying nirviReportUnexpectedCaseInternalError (String).vi  (5.58 K)
Deploying nirviReportUnexpectedCaseInternalError (U32).vi  (4.72 K)
Deploying _nirio_device_readBlock32.vi  (14.41 K)
Deploying _nirio_device_attrGet32.vi  (13.85 K)
Deploying nirio_IsItOKToDownload.vi  (7.07 K)
Deploying nirio_MiteNTDeviceFamily.vi  (5.30 K)
Deploying Format Message String.vi  (7.35 K)
Deploying General Error Handler CORE.vi  (51.02 K)
Deploying General Error Handler.vi  (13.19 K)
Deploying Simple Error Handler.vi  (10.01 K)
Deploying nirio_CheckDriverVersion.vi  (10.58 K)
Deploying _nirio_device_attrSet32.vi  (13.62 K)
Deploying nirio_Download.vi  (29.31 K)
Deploying nirio_ConfigureRegisterAddresses.vi  (7.11 K)
Deploying nirio_CleanUpAfterDownload.vi  (6.22 K)
Deploying nirio_PrepareForDownload.vi  (6.44 K)
Deploying nirio_EnableInterrupts.vi  (13.76 K)
Deploying nirviRIOSetUpMiniMite.vi  (31.23 K)
Deploying nirio_Open.vi  (14.93 K)
Deploying nirio_Close.vi  (10.95 K)
Deploying nirio_DisableInterrupts.vi  (11.10 K)
Deploying nirviIntfOpen_cRIO-9102.vi  (85.54 K)
Deploying nirviIntfClose_cRIO-9102.vi  (12.24 K)
Deploying scale freq and duty.vi  (4.46 K)
Deploying XDNodeRunTimeDep.lvlib 
Deploying XDNodeRunTimeDep.lvlib:loadlvalarms.vi  (5.47 K)
Deploying sensor math.vi
Failed to download sensor math.vi
LabVIEW:  Resource not found.
LabVIEW:  Resource not found.
LabVIEW:  Resource not found.
LabVIEW:  Resource not found.


Download completed with errors.

That error message is not particularly helpful, does anybody know what my problem could be?  Or how I can troubleshoot it further?  Is there some detailed log where I can look for more information on the error?

Thanks in advance for any help!

[DanRichards]

Hi Nullified,

I did a quick search on my computer and could not find the file, "sensor math.vi." Do you have any special toolkits installed, or was the program you have created on a computer that has additional toolkits? Perhaps this VI is a subVI that you created? Can you perform a search for this file on the machine on which you developed your code?

If your program is very simple, I would recommend re-writing it only with functions that are as simple as possible; and feel free to include a screenshot for us.

There is the possibility that the sensor math VI is tucked away in a library somewhere and that's why I couldn't find it in the search. I'll have to look into that further.

Regards,

Dan Richards

[Nullified]

Hi Dan,

I tried making a new VI to do the same thing hoping it was just some wierd glitch, but I still get the same error.  I remade the sensor_math.vi with a new name pwm_out.vi and I also seperated the FPGA code into two seperate VIs hoping that might help (since I seperated the square wave generation code from the code that reads the inputs/writes the outputs).  But I still get the same error.  It actually works if I get rid of the bottom while loop in "pwm_out.vi", but I need to be able to read from the sensors as well.

Thanks,

David

[Nullified]

Also here's a screenshot of the FPGA code.

Also the wierd part is that sensor_math.vi (or now pwm_out.vi) is the VI itself that I am trying to run, and it fails to download it.  I'm guessing it has something to do with my FPGA code, but I really don't know.

Message Edited by Nullified on 10-15-2008 10:57 AM

[Nullified]

So if I change my code to the following (attached as "pwm_out_modified.png" ) then it runs fine, so I'm fairly sure it has something to do with my FPGA code ("fpga.png" shows the code that I removed).  Any ideas what might be wrong with my FPGA code?

Thanks,

David

Message Edited by Nullified on 10-15-2008 11:02 AM

[Stephen_Moore]

Hi Nullified,

I think that you might have a problem with understanding how the FPGA works.  You can ONLY have one FPGA bitstream operating at a time. 

You appear to have TWO fpga vis fpga.vi and fpga_square_out.vi in your project.  You can only run one of them at a time, unless they are sub vis called from a main vi.  This does not seem to be the case according to your project file snapshot.  Your RT code may appear to be OK because you are referencing each loop to a different fpga bitstream however it will fail to compile as you can not run two bitstreams simultaneously. 

I think that all you need to do is have your two fpga vis combined into a single vi, compile it and then in your RT you just reference the one new bitstream that contains all the code.  FPGAs work differently as a bitstream image that is overlaid onto the gates, if you need several loops they should all be in the same vi. 

If you really need vis then they have to run sequentially and you have to load and run one bitstream then unload it and load and run the next.  I am sure that this is not what you want to do here.  Once the code is generated the FPGA loops will be totally independent of each other.

Cheers

Stephen

[Nullified]

---

Stephen Moore wrote:

Hi Nullified,

I think that you might have a problem with understanding how the FPGA works.  You can ONLY have one FPGA bitstream operating at a time. 

You appear to have TWO fpga vis fpga.vi and fpga_square_out.vi in your project.  You can only run one of them at a time, unless they are sub vis called from a main vi.  This does not seem to be the case according to your project file snapshot.  Your RT code may appear to be OK because you are referencing each loop to a different fpga bitstream however it will fail to compile as you can not run two bitstreams simultaneously. 

I think that all you need to do is have your two fpga vis combined into a single vi, compile it and then in your RT you just reference the one new bitstream that contains all the code.  FPGAs work differently as a bitstream image that is overlaid onto the gates, if you need several loops they should all be in the same vi. 

If you really need vis then they have to run sequentially and you have to load and run one bitstream then unload it and load and run the next.  I am sure that this is not what you want to do here.  Once the code is generated the FPGA loops will be totally independent of each other.

Cheers

Stephen

---

Hi Stephen,

I previously had the contents of those two FPGA VIs in one singel VI (two seperate while loops), which gave me the same error as I mentioned.  I'm not too familiar with how sequences work, but would this work (attached as "fpga_new.vi" )?  I'm compiling it now, so I'll try it once it's done.

Thanks,

David

[Nullified]

I'm sorry I keep adding more to this thread, but I've narrowed the problem down.  It appears that whenever I actually try to access one of the analog inputs from my FPGA file is when it get's the "resource not found" error.  I have attached a screenshot of my pwm_out.vi, if I remove the bottom read/write control, or if I don't at all use any of the analog inputs, it runs fine.  But as soon as I add the analog inputs it fails...

Any ideas?

Thanks,

David

[JMota]

Hi David,

I haven't read the whole thread, but seems that you have been able to isolate the problem to be only when using fixed-point data type controls/indicators with the FPGA interface. Is that correct?

>>I am using a CompactRIO 9002 and LabVIEW 8.5 

What version of RIO are you using? If you are using RIO 2.4 (or later) with LV 8.5 (not 8.5.1), installing LV and LV RT 8.5.1 should fix the problem (or you will have to do a data type conversion so you transfer integers and not fixed-point numbers - you just need to make sure the cast does not truncate the decimal part of your numbers)

If the problem is not isolated to Fixed-point data type controls and indicators, then disregard my comment. 

Message Edited by JMota on 10-15-2008 04:59 PM

[Stephen_Moore · Accepted solution]

Hi David,

You might be treading on dangerous ground with your fpga code, both old and new.  You are using the modules in what is known as "calibrated" calibration mode i.e. fixed point math.  Your fpga square wave generation is using integer math which is normally used when the modules are operating in "raw" calibration mode. To change the calibration mode you need to right click on the module and select the mode youwish to use.  I do not suggest that you do this.

What you NEED to do to ensure correct operation of your fpga vi is to make sure that you are using U32 math wire required and then convert the U32 to a FXP using the correct encoding ( whether it is signed, word length, and integer length).  In your case the 9263 requires a signed, 20bit word length, 5 bit integer length.  Insert a  FXP conversion between the square wave generation and either create a FXP constant of the correct type (or use a correctly set up control from one of the other 9263 channels [AO0 or AO1]) and wire it to the fixed point type node on the conversion OR define the fixed point conversion by right clicking on the output node and making the correct settings in the pop-up box.

As for your new fpga code, I am not sure why you have used a sequence structure your reading of 18 channels on the 9205 will take 144 microseconds, and each write of two channels on the 9263 will take 5 microseconds.  I have not worked out how long the square wave generation will take.

I do not understand your most recent question. 

>>"I have attached a screen shot of my pwm_out.vi, if I remove the bottom read/write control, or if I don't at all use any of the analog inputs, it runs fine. 

>>But as soon as I add the analog inputs it fails...".

Have you created a new bitstream from your fpga_new.vi and referenced it in your pwm_out_new.vi on the RT?

It is hard to second guess what you are showing in the screen shots.  If the project is not too big then perhaps you could post it here. 

As mentioned earlier, by JMoto, software versions help as well.  Check in MAX what you have on your PC and also on the cRIO 9002 to make sure that there is no mismatch.

Cheers

Stephen