Compilation stops at low level synthesis

[Gautam Dee]

Hi

I am workign with NI crio 9014 and labview 8.5.1 and was compiling my target FPGA. For some reason I had to stop the server and abort it, but when I tried to compile it again, the compilation stops at a stage of "low level synthesis" and hangs up there. I tried to do everything from building a new project with the files and what ever I could, does anyone know why this happens and how it can be fixed ? This has hapenned too many times now and I need a fix.

Thanks

Tamanna 

[Eli_S]

Hi Tamanna,

Did this problem only start happening after you stopped the compile server that one time, or did this happen before that as well. Also, does that happen all the time now or just at random times?

I have never heard of this happening before and I suggest doing a repair of the LabVIEW FPGA module to see if that changes this behavior.

[Aaziee]

Hello,

we experienced the same problem also with cRIO 9014 and LV 8.5.1. We tried to compile two very simple programs but it took over 21 hours after that we stopped the compiler (the day before *something* happened we could compile with no problems). Screenshots of the examples are in attachements. Similar behaviour. The compiler did, however, get beyond Low level synthesis part but only after several hours. Attached is also compiler message got after 21 hours of compilation of Example2 (on rather powerful computer that used to compile similar programs in 15 minutes or less) after which we stopped the compiler. We tried repairing FPGA installation, then reinstalling - did not work. What could cause such behaviour? What can we do to try get things to work?

Thanks

Ozren

[TLE]

I have seen this problem with 8.2.1, 8.5.1, and 8.6.  The Compile Server stops updating its Details window, sometimes after 45 minutes or so.  I have to kill the Compile Server with Task Manager and then re-boot my computer.  Usually it will compile successfully the second time but not always.  This is very frustrating.

[Eli_S]

Hi,

I have actually seen this before in situations where the DMA FIFO has been configured to be deeper than what the target supports. Can you verify what the configuration for your FIFO is? Can you make it smaller and see if it compiles?

[Aaziee]

Hello,

Success!

It definitely has to do with FIFO depth. At first we configured FIFOs depth to 70000 (28 channels*2500 points=70000) from LabVIEW Project Explorer and the computer coerced to 131071 (2^17-1). Then  when we tried to compile it- the "long time compile" problems begun. But then we set FIFO depth to 8191 (with FIFO set to Target to host DMA, of course) and it compiled in a normal time (10 minuites or so)! We then set FIFO depth programatically from RT to desired 70000 and it worked!

But this 131071 is the depth FIFO should support (we set FIFO depth from RT to 210000 = 3*70000 and it worked fine). So we are bit confused why it created us problems before...

Anyway it worked - thanks Eli_S! We would have never thought of that 🙂

Ozren

[yuval_yohai]

Same problem with me. Version 8.6 when copiling the FPGA with FIFO too big.

I have used the same solution. Reconfigured the FIFO depth from the RT vi.

Yuval

[Ruhmann]

Just an FYI, the FIFO depth you set on the FIFO under the FPGA target in your project is the FIFO depth on the FPGA.  The FPGA doesn't have a whole lot of memory and the exact amount should be documented in the manual that came with your backplane (I just saw it in the data sheet for the 910x backplanes under RAM).  Once the FPGA runs out of RAM resources, the tools will try really hard to create more RAM out of the remaining gates on the FPGA.  That's why you observed the tools hanging (they weren't hung, the tools were probably just thinking really, really hard for a very long time).  A FIFO that is 8k deep should be more than enough for most applications.  When you set the FIFO size on RT, you're setting up how much RAM on the controller (the RT side) you want to use for the FIFO.  The backplane will transfer data from the FPGA FIFO to the RT FIFO whenever there's data available and the bus is free (well, that's an overly simplified way to explain it, but I think it gets the point accross).  Therefore, you don't need a FIFO depth on the FPGA side that fits all your data.  That's overkill.  On the otherhand, the RT side should be large enough to hold the amount of data that is pushed into the FIFO between the FIFO reads on your RT VI.  The FPGA FIFO just needs to be deep enough to handle busts of data that are pushed into the FIFO faster than the PCI bus (throughput of the PCI bus is typically 60 MB/s from our internal tests) can move the data to RT.