DRAM : data corruption @ 100MHz

[CyGa]

Tannerite,

Your XLS looks fine.

The ultimate solution to get more than 500ms of acquisition (#200 Mo) was to directly send them trough DMA. Thanks to the PXI bus + MXI 4 transfer it went all fine.

So the DMA transfer is more than good.

Moreover, the timeout of DMA_ToHost is handled ! Please find attached a print screen of the code ('transfer to host' part) where you can see that the timeout is handled.

The timeout of FIFo_Debug DMA is not handled, because it returns valid data (1000 pts). Also proving that the DMA transfer works fine @ 12.5 MHz (100Mhz / 8 pts).

Have you test my code on a real target ?

[tannerite]

Hi zyl7,

I tried the posted code on some of our hardware here and I believe the Request Data method was filling up to its maximum (32 in your case). Once that happens the RFI flag shows FALSE. When this happens your code sits in the loop and hits a case structure which just sits there and does not process data. I believe this has to do with no implementation of the 4-Wire handshaking in your algorithm that sends the upper and lower 64-bits. I have attached an example that does implement 4-Wire handshaking and the expected data matches the actual data for a simple test of 1000 points.

When running your code, I changed the maximum outstanding requests and saw different behavior as well so I am fairly confident what was explained about was actually happening with the RFI flag. Please check out the attached example. It is not using your exact hardware so you will need to modify it a bit but it has the same amount of DRAM and the same functionality in terms of memory allocations. I hope this helps!

Best,

tannerite

[CyGa]

Hi Tannerite,

Can you convert the VIs in LV 2011 so I can open them ?

I do not have LV2012 installed yet...

[tannerite]

I saved this project for a previous version, which is attached below.

-tannerite

[CyGa]

Hi Tannerite,

What a fairly complex code just to read a DRAM @100MHz...

"I tried the posted code on some of our hardware here and I believe the Request Data method was filling up to its maximum (32 in your case). Once that happens the RFI flag shows FALSE. When this happens your code sits in the loop and hits a case structure which just sits there and does not process data."

You are right when you say that when RFI turns False my loop just do nothing waiting that the RFI flag comes back to true. So, for me it does not explain why "I" miss a 64-bit element.

"I have attached an example that does implement 4-Wire handshaking and the expected data matches the actual data for a simple test of 1000 points."

Why is the Input Valid of the Request Data node is linked to the DMA Timeout ? It is not because a timeout occured somewhere that the Input Valid of the request should be placed to true... Input Valid should be linked to something that invalidate the request. What is the matter if the Input Valid is always set to True but the adress requested isn't incremented if the DMA is in timeout ? Is there any difference ?

[tannerite]

Zyl7,

The Input Valid of the Request Data node is linked to the 4-Wire Handshaking state machine's Output Valid. This state machine handles the handshaking from the upper/lower 64-bit toggling and logic to send the data through DMA properly. In a way, it is indirectly tied to the DMA timeout; this lets the handshaking state machine know that the algorithm, including the DMA Write, is done successfully. This alerts the state machine which takes the appropriate action.

-tannerite