Data Acquistion problems with sbRIO 9631

[EdwinM]

I just started using the sbRIO-9631 board. I have used a small amount of labVIEW before and have read through the CompactRIO developers guide which was useful for some parts of my task.

The beginning of my project requires a user to be able to turn on 2 of 4 LEDs at individual times, 1 for reference and the other for measuring the data.

So to start off I created a button for each LED to determine which LEDs the user wants on, which can also be changed while the program is running. This then triggers how long the LED stays high, stays low and how much output voltage is produced per LED button pushed (all set by the user). The output is given to the AO ports and displayed on an oscilloscope. This works, it may not be the best way to do this or the best looking code, but the screen shot is below. (Each LED in their while loop is in a different state of the state machine, for reference, these are the only 4 states available)

Host.vi

So from here I would like to acquire two of these analog output channels through the analog input channels on the sbRIO board.

I have tried, with an external wire, wiring the AO port to AI port directly and using the on board DMA-FIFO, but all I get garbage on the waveform chart.

Questions:

1. Could it have something to do with the sampling rates between the RT and the FPGA? (here is the image of how I set this up)

Host.vi

2. I have not seen any examples of this sort of I/O configuration yet, has any one else tried to do this?

A basic example that could help could be, generating a sine wave on the analog output - wiring externally the AO port to AI port - using a FIFO - and displaying this on a waveform chart/graph. (I have tried to do this but it did not work either)

3. Is there also a way of  switching between the channels that are acquiring data while the the program is running depending on which 2 channels the user has selected?

4. Or will the user have to stop the program, decide on the next two output channels and then using the same analog input channels to acquire data?

[alcava.cr]

Hi there, as a starting point I recommend this series of videos. Plus, FPGA VIs run at hardware level so remember to limit the use of front panel objects since there is no direct contact to users, instead read digital lines and pass around the data acquired. Now to answer your questions:

1. Check your FIFO settings, configure it to transfer a fewer number of elements like 5-10 for the testing. Track down the garbage data, is it appearing before or after writing to the FIFO? Run the FPGA VI and check the data using probes until you find the source of the issue.

2. To be honest, me neither. I would focus on data acquisition and triggering at the FPGA level and leave data manipulation, file IO and other for real-time or windows level programming. If you are looking for examples open the NI Example finder and type the module numbers (9205 and 9263) on the search.

3 & 4. Use the case structure concept that you are using at the host, simply decide when to show, or not, the information to the user. No need to stop the program or the acquisition.

[EdwinM]

Hi Alejandro,

Thank you for replying to my message. I have watched those videos before, watching them again after coding with the FPGA gave me a better understanding. After writing the previous message and those questions I thought it would be a good idea to simplify my design to read and write only one analog channel at this stage then expand on this later. Here is the simplified version if you are interested.

FPGA.VI

HOST.VI

The HOST.VI setting were set to: LED1 on timer = 4000000 ticks, LED1 off timer = 4000000 ticks (both 100 ms), Voltage LED1 = 3276 bits (~ 1Volt), Sample delay rate = 800000 (ticks), number of elements = 10 and timeout = 0.

I took your advice and used the digital lines to write and read when a button is pushed. This meant that I could now fully control the program without having the FPGA VI running at the same time. Is that what you meant by limiting the use of front panel objects on the FPGA VI?

I then checked the fifo settings, sampling rates and configured the number of elements to be transferred to 10 as you suggested. This all worked perfectly and the program outputs the correct signal on the waveform chart. So I'm pretty sure the problem with the last program was that I was running the FPGA VI at the same time and sampling rates of the loops were incorrect. That was why I was getting strange looking output signals.

From here I should be able to manipulate the data on the real time host VI as you have also suggested and will expand the program for the other analog output and input channels. If I get stuck again should I post here or start a new post?

Do you have any other tips?

Your help has been greatly appreciated, thank you very much.

Edwin

[alcava.cr]

Hi, I'm glad to hear that you are making some progress. Here is an explanation of what I meant by Limiting the Number of Front Panel Objects in FPGA VIs. Regarding running the FPGA VI, seems like you are missing the Run Method. Plus, the top loop on the FPGA VI can be replaced by a physical button connected to Port8/DIO0 like shown in figure 23 from the SbRIO User Manual.

If you find yourself stuck again I recommend looking on the community for answers first. Most of the times you can find knowledge bases, articles or discussions that can help you. If you can't find anything you can create a new post.

Tips & trick...well, you can check the LabVIEW FPGA Module User Manual. Also, there is always the option of taking one of our training courses. I hope this helps.