Sorry for my late reply. Actually, I am not using any IO/module clock...In fact, the code I am
using is an extension of the sample "VST streaming project" given in NI5644R.. I am using
a constant "clocK" wired to SCTL...
For everybody's reference, I am sharing screenshots of the code I am using...A brief
description of the attachments is given below..
1. "Top_level_FPGA_part1_modification.png": In a 120MHz SCTL loop, a FPGA sub-vi reads
from a block memory FIFO.. Actually, the reading is actually done when the input
"read_stream" is enabled.. (see details in read_from_fifo_true_case.png)
2. "Top_level_FPGA_part2_modification.png": A 40MHz SCTL, in which a FPGA sub-vi is
invoked to write the output of a convolution to the block memory FIFO.
3. "target_respone_fpga_block_FIFO_modification.png": A convolution output from a filter is
written to the block memory FIFO whenever the convolution output is available..
"ReadBlockFIFO" VI (encircled in Top_level_FPGA_part1) is invoked in a 120MHz SCTL.
4. "read_from_fifo_false_case.png": When the "read_stream" input of this vi is false,
transfer of data from block memory FIFO to another FIFO ("Filter to Generation") takes
place.
5. "read_from_fifo_true_case.png": When the "read_stream" is true, data is read from
"Filter to Generation" FIFO and passed on to the subsequent interpolation chain in the
120MHz SCTL...
I hope the attachments give enough clarity of what I am trying to do... If there is a need
for further clarifications, please do not hesitate to ask...
Meanwhile, I will try out discarding the 40MHz loop, and instead do the convolution
in a 120MHz SCTL, but at every 4th clock cycle...
With best regards,
S. Kumar Raja
