ERROR:Xflow - Program xst returned error code 19

[acrocker]

I'm labview ver 8.5 when I compile my FPGA code I get the following error

ERROR:Portability:3 - This Xilinx application has run out of memory or has encountered a memory conflict.  Current memory usage is 2091028 kb.  Memory problems may require a simple increase in available system memory, or possibly a fix to the software or a special workaround.  To troubleshoot or remedy the problem, first:  Try increasing your system's RAM.  Alternatively, you may try increasing your system's virtual memory or swap space.  If this does not fix the problem, please try the following:  Search the Answers Database at support.xilinx.com to locate information on this error message.  If neither of the above resources produces an available solution, please use Web Support to open a case with Xilinx Technical Support off of support.xilinx.com.  As it is likely that this may be an unforeseen problem, please be prepared to submit relevant design files if necessary.
ERROR:Xflow - Program xst returned error code 19. Aborting flow execution...

I have 2 GB of ram and have increased the virtual memory.

I don't think that it is my code. The problem occurrs after I have added 2 FIFO, one is Host to target and the other is target to host. My code will compile without the FIFOs and I can compile my code with just the part that has thr FIFOs but together I keep getting this error.

I als checked the support.xilinx.com site it did not provide any information about this error.

[Captain_Kirby]

Hi acrocker,

The error you are seeing can be broad in its possible causes. To understand what is giving us problems, I'd like a bit more information. What model of hardware are you using (what controller, chassis and modules?) At what point does this error occur? Do you receive this message right after starting the compile, or does it happen after an extended period of time? If it does take time, how long? Before you added the DMA FIFO's (while the code still compiled and worked,) how long did your compile usually take, and what amount of the FPGA was used when the compile was complete? What is the depth of the FIFO's on your FPGA (how many elements do their buffers contain?) While the program compiles, check the system monitor to see what amount of RAM is being used, especially during the time just before the error occurs.

If you could try to find the answers to these questions and post back, it would help diagnose where this error is originating from. Also, any screen shots of your code or error messages may prove to be helpful.

Sincerely,
Asa Kirby
Applications Engineer
National Instruments

[acrocker]

I am using cRIO-9012 with 8 9401 digital I/O modules. With the FIFO removed the it takes about 1hr to compile. The error occurs at about the 1hr mark. It happens after Loading device for application Rf_Device from file '2v1000.nph' in environment C:\NIFPGA85\Xilinx.
INFO:Xst:2691 - Unit <DualPortRAM> : The RAM <Mram_iRAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <oDataOut>. With out the FIFOs the code compiles and uses 38% of slices. Host to Target FIFO is 255 elements and the Target to Host FIFO is at 15 elements. I did notice that there is a large difference in intermediate files created 3000+ with FIFO and ~1500 with out them

[Captain_Kirby]

Hello again acrocker,

Looking at your screenshots, your implementation for FIFOs seems to be correct. I can’t say for sure without seeing what the rest of the code looks like though. There are still too many possibilities to say for sure where your problem is coming from. Could you post a copy of the compile reports for both a successful compile (without the FIFOs) and an unsuccessful compile (with the FIFOs.) There is still a good possibility that your code is just very complex, and in order to compile it completely, you’re going to need more physical space. Judging by your first post, the program has already used all of your available 2GB of ram. I'm not sure why increasing virtual memory didn’t help, but it’s possible the compiler was unable to use the added space due to the size of single files.

There is also a possibility that you have run out of ram on your FPGA. Judging by your last post, the compiler was attempting to make a ram block, possibly for the FIFO. If the FIFO buffer size is larger than the available RAM, you will receive an error. What model of backplane do you have paired with this controller? Is it a 1 million gate or 3 million gate units? Also, the size of the buffers you posted in your last reply seems to only be the amount of items you are putting into the buffer, not the actual size of the allocated buffer to be created. When you first created the FIFO through the project explorer, in the "FPGA FIFO Properties", there is a section under the type of FIFO choice called "Data Properties". In this section, you can find a control called "Depth". That’s the pre-allocated FIFO size in memory on the FPGA. What size is chosen for your two FIFOs?

If you could provide this extra information, I'll see what I can find out.

Thanks!
Asa Kirby
Applications Engineer
National Instruments