FFT of analog input (NI-5761) using 7966R FlexRIO

[aish_2489]

Hi everyone,

I'm relatively new to LabVIEW FPGA and I want to do an FFT of an analog input (NI-5761 adapter module) using the Target FPGA 7966R FlexRIO and then display the frequency spectrum on the host PC. 

There is an example FFT Co-Processor under the FlexRIO examples that's very close to what I want. However, instead of writing a simulated waveform to a host-to-target FIFO, I want to get the input signal from my analog port. My approach was to 1) in the host vi, deleted the loop that sends out a simulated waveform 2) in the fpga vi, replace the Host-to-Target FIFO with a I/O Module Analog Input Node.
I gave the modifications a try but i get timing violation errors when I compile the fpga vi.

LabVIEW version is 2012

Any help would be greatly appreciated. Thanks!

[David-A]

None of your screen shots show what the timing violation is. Try clicking the 'investigate timing violation' button to get more debug info. 

Not sure how you configured your fft, but its possible that the data clock domain you've placed it in is running faster than the data path on that fft will allow. Tough to say without seeing what is the source of the timing violation. If that is the case you can try configuring it with additional pipelining at the cost on increased fpga utilization and greater latency.

Another option is changing the clock source for the timed loop that the fft vi is running in. Looks like you're using IO Module Clock for all the timed loops. If you use a slower clock for the fft vi then it may meet timing, but because it runs slower you won't be able to stream continuous data to it, instead you'll have let through finite records that can fit in the target scoped fifo and process all the data those before you let more data through. 

[aish_2489]

Hi,

Thanks so much for your response.

Yes I lowered the clock source from I/O Module (running at 125 MHz) to FPGA 40MHz onboard clock. FFT  block is running fine now,but my IO Module NI 5761 is still sampling at 125 MHz.Could anyone help me out as to how can I effectively take the FFT when my IO Module clock rate(125MHz) is greater than my FFT block clock rate(40MHz).Are the samples getting lost when I am using a while loop with a timer to acquire input samples from the IO Module?

I have attached my fpga as well as host screenshots.

[SamuRei]

I'm not sure how helpful it'll be in your case since the clocks aren't an even division of one another, but the FFT Express VI that you're using has an option for "Single Input, Multiple Samples". So if you can pass it an array with 3 samples per iteration, you'll probably be better off than only catching every ~3rd sample.