Hi Guys,
I am currently trying to acquire voltage and current measurement data from an Analog Input Module 9201. The intention is to sample at 20kHz. I am using a Compact RIO 9022 with a 9113 chassis. I know I need to create a FIFO as a buffer between the FPGA and real time controller. The FIFO created in the project is a Target to Host -DMA (im assuming this is correct) with 12000 elements and a data type of FXP, signed 16 bits. In my FPGA VI, I set the loop to execute every 50us each time gathering 1000 samples from each of the 6 channels.
For testing purposes, I am currently using a signal generator to generate a pure sine wave of 50Hz with an amplitude of 5.
On my Real Time VI, im not sure if I configured the FIFO correctly. I used an Invoke Method to configure a FIFO with a depth of 40000. The VI loops at 100ms, each time acquiring 6000 samples ( 6*1000) of data. When I view the graph FIFO tester, the results were erratic, with moments of it showing a badly sampled stepped sine wave.
Also, I am intending to phase shift the signal using the Fourier based phase shifter shown in my VI. Instead of only phase shifting it, the signal is offset as well. I am not sure what is the problem with this part. I tried using a Hilbert Transform phase shifter ending up with the same problem as well.
Would really appreciate if I could get some help regarding this matter.
Thanks
