FIR Filter (Xilinx Compiler) Issues

[bhartman2]

I am attempting to use the Xilinx FIR Compiler to implement a simple low pass filter. I have a noisy sinusoidal input signal, and want to filter out everything above about 150 Hz. I generated an equiripple filter using MATLAB that works perfectly for my application using simulated data, however when I try using the FIR Compiler and running the filter on my FPGA, the high frequency noise is correctly filtered, however both the magnitude and phase responses of the filter are incorrect.

Specifically, what should be happening:

1. Magnitude Response: around 0dB for my whole range of interest (40 - 100 Hz).

2. Phase Response: linear phase offset for my whole range of interest

What is happening:

1. Magnitude Response: about -8dB

2. Phase Response: nonlinear

I have already posted about the compiler configuration on the Xilinx forums, but have not had much luck yet. It is also likely, however, that the issue is with the organization of my Labview Code. I am not all that great with Labview FPGA and may have arranged my code incorrectly in terms of the different loops. All I want to do in this particular piece of code is to sample the signal at 10 kHz, run it through my filter, undo the (what should be constant) phase offset, and then output both the original and filter signals. For now since I am still trying to debug, I am just generating the input using a waveform generator and then adding noise. I tried looking at this NI white paper for help, but the pictures of their code are so blurry that it is difficult to see how their loops are actually arranged: http://www.ni.com/white-paper/13698/en/.

I've attached a picture of my code, the MATLAB magnitude/phase plot, plots of the simulated MATLAB signals, as well as a copy of the VI itself.

Thank you for your help,

Brett

FPGA VI:

MATLAB Phase/Freq Response Plot:

Simulated Signals (Original and Filtered):

[alyssa.h]

bhartman2,

Would it be possible for you to post a picture of your FIR Compiler configuration? Just double click on the FIR Compiler to pull it up.

Thank you, 

Alyssa H

National Instruments

[Kallis]

The FIR VI seems to have a valid/ready boolean output. In my opinion, you should use that to decide whether the data coming out is valid or not?

[bhartman2]

Alyssa,

No problem -- here are the 4 screens on the compiler configuration window. FYI this filter is slightly different that the one in the MATLAB plot I posted originally: same type of filter, passband, and stopband frequencies, but just using more coefficients -- wanted to see if I could get any improvement that way, but no luck. It may also be worth noting that in my filtered response on the FPGA, I am indeed seeing a sharp rolloff in magnitude at the frequency I expect based on the filter design (starting around 150 Hz), just that the magnitude response is still around -8dB all the way up to that point when it should be near 0dB, and the phase is nonlinear. Thanks for taking a look.

[Kallis]

In your initial post, you had mentioned that sampling frequency is 10 KHz.

However, in the FIR compiler the Input sampling frequency is chosen as 0.1 MHz (100 kHz). 

May be that is the reason why the filter response (in the filter analysis section) doesn't match with the frequency response you are expecting. It might also be the reason why you see lower stopband attenuation (-31 dB) compared to the MATLAB plot (around -55 dB) as the transition band becomes 10 times steeper with 100 kHz. 

Try with an input sampling frequency of 0.01 MHz. 

[bhartman2]

Sorry, I forgot to mention in this version of the filter that I posted the configuration images for, I had changed the sample frequency of the filter to 100kHz in addition to the increase in filter order, so the configuration frequency is correct in this case. I have attempted to design versions of the filter with both frequencies, but the result was the same. Here is the plot of this filter from MATLAB (zoomed in a bit), which matches the -31 dB stopband attenuation seen in the FIR Compiler plot:

[Kallis]

OK, no issues. 

Actually, if all you are interested in is filtering out 150 Hz and assuming no higher frequencies that can cause aliasing,  you do not gain anything by having 100 kHz sampling frequency. 

In fact it can makes things more challenging due to the fact that the transition band is so narrow resulting in a huge filter order that you have currently.

If I were you, I would just sample at a rate of around 10 times the highest frequency in my signal, and design the filter accordingly. 

From the MATLAB plot, it appears that the stopband edge is at around 0.005 PI. 

With 100 kHz sampling, the stopband edge will be around 250 Hz. 

What I understood from the first post, you expect the passband edge at 100 Hz and stopband edge is at 150 Hz (?)

You might also have some sampling issues.

It might be that the loop is not able to run always at the rate that you expect it to run.

This might be causing some nonuniform sampling. 

I would recommend to try with a much lower sampling frequency and a significantly lower order filter. 

Also, placing the AI code inside an SCTL which runs at the sampling frequency might help. 

Unfortunately, I do not have an FPGA target/module to try out. 

[bhartman2]

Hm. I tried reducing the sampling rate and filter order to 1kHz and 100, respectively, but am seeing essentially the exact same behavior: magnitude reduction of -6dB and nonlinear phase.

I am sure that in both cases, the loop is executing at the specified rate (in my original post with the image of the fpga vi, you can see there is a "real loop rate" indicator that is verifying the time it takes for the loop to complete, which does match my specified rate.

The cRIO modules I am using for my input unfortunately do not support use in SCTLs, so I cannot try that out.

Another thing I am noticing is that the "rfd" port is actually always reading false implying that it is "never" ready for data, yet the filter itself is still functioning 90% correctly in the sense that it rolls off at the correct stopband freq, still filters out the high frequency noise, and has constant (though incorrect) amplitude response in the passband. Not sure what to make of this or why it would never be ready for data. 

[IvanRyger]

Dear colleagues, I am having also some issues with XILINX FIR compiler.

I had to avoid the Labview vi generation from Digital Filter Design Toolkit because it always created the multiplier-accumulator scheme, that was not fast enough.

I would like to have an optimized FIR filter (~50 taps equiripple design) running at 160kHz on three-channel data (my top level clock is 40 MHz).I compiled the FPGA code, but it does not send me any data to the output of the filter. 

I haven't defined any input clock signal, nor asynchronous reset during run of xilinx IP tool. The labview code always hangs up at the FIR compiler function.

[IvanRyger]

I am also adding the configuration of the XILINX IP