FPGA Slice Allocation

[Robert_Hoffman]

Hello,

I am working on a project that is using a CRIO-9101 chassis, with 4 module slots and 1M gates.  I keep running up against the slice limitation (5120), for what I think should be a fairly simple program.  I have optimized the compiler for area, removed any arrays, simplified the code as much as possible, and started pulling parts of my FPGA code out to the RT application.  However, it would be really nice to see what parts of my code are taking up the most room.  Is there a way to see the mapping from the compile report to see how many slices each part of the code is taking up, so that I can prioritize what parts of the code to tackle next?  It might be buried in the compile report, but I am not sure.

Thanks,

Rob

[MattP]

Hi Rob,

It sounds like you've already taken many of the steps I would recommend to solve the overmapping problem on the FPGA compile, but there are a few additional options I'd like to direct you towards.  We have a good KnowledgeBase article on our site that lists some of the best optimization techniques, most of which you've done well already.  The page also includes, and I think this is more what you are looking for, a document detailing the FPGA utilization for each type of element, both inside and outside a Single-Cycle Timed Loop.  You gain significant area savings when using the SCTL since it can strip out all of the additional code that we use to ensure dataflow functionality.

[Robert_Hoffman]

Matt,

Thanks for your reply, that article is very useful, especially the table in the article.  It would be really nice to have something like the execution trace toolkit for the FPGA, looking at timing and memory (slice) usage.  I find myself struggling to decide what code to move over to the RT, so that I don't overload my RT controller, but can still fit everything critical on the FPGA.

This project was my first real experience with FPGA, and I now have a much better idea for future projects about what the limitations in terms of complexity are when you move to the FPGA!

Rob

[MattP]

Hi Rob,

That's an excellent idea - I know when I've worked on FPGA projects in the past, that would be something very useful to have.  My best recommendation to you would be to let our development team know directly that this would help you - you can file Product Feedback at www.ni.com/contact.  The more information they have as to what would benefit you, the better we can make the next release meet your needs.

As a general rule of thumb, a calculation that requires high complexity (including floating-point calculations) or file I/O would go on the RT, whereas a calculation requiring tight timing and hardware I/O would go on the FPGA. 

If you run into any more roadblocks, just put up a new thread and we'll help out!