FPGA memory access in a state machine in a SCTL

[arnomarc]

Hello,

May any body help me in this subject?

Here is my material :

 - PXI 7953R + NI 6581 (I/O) developping with Labview 2009.

I have to control outputs and read inputs with high precision.

The solution i tried was to make boards of clusters as commands at the front side but it takes too much space (LUTs).

Then i want to put the informations in memory. The user have to put informations in the memory before running the FPGA.

I can't use FIFO because I have to take information the first information after the last one (loop).

The question is :

Can I get information from memory when i work in a state machine in a SCTL?

Is it possible?

Thank you for answering.

Arnaud

PS: sorry for my english...

[BenjaminR]

Hello arnomarc,

Thanks for posting on National Instruments forum.

It is quite difficult to answer your question saying Yes or No. It will depend what kind of memory you want to access inside your SCTL. If you use a part of FPGA to store your data it will be possible to implement the memory access in the SCTL. You should find in the LV Help information about the number of tick takes by a function. An SCTL should execute in 1 tick.

[arnomarc]

Hi Benjamin,

Thanks for answering me,

I have to access memory inside the SCTL.

I found the solution :

 - Add functions to add values in RAM memory (1 function per board of values).

 - Get informations in other SCTLs. => the advantage is that it is using few LUTs and I have saved 70% of Flip-flops.

 - To get informations from the RAM, I have used pipeline functions, it works very well!

The problem was that I have not a lot of experience working on FPGAs. I learn a lot of things, it's good!

See you,

Arnaud