Real-Time Measurement and Control
High speed acquisition on a cRIO
Nick,
The transfer rates listed in that article seem to be a bit on the conservartive side, especially for the PXI controller. It is true that the
tranfer rate you will achive from FPGA to RT controller on cRIO will significantly depend on the rest of the code that will be running on the RT controller. In addition the transfer rates will vary with the different cRIO controllers and their different processors.
However, even for the older cRIO controllers if you do not do a lot of processing on the RT side, you should be able to achieve a data transfer rate around 1 MB/s, and possibly higher for very simple RT programs or newer cRIO controllers. To achieve these transfer rates you will always have to use the DMA FIFOs on FPGA and RT, so it will be a bit different from your previous programming.
Here's a number of additional useful articles:
Stream to Disk Benchmarks for cRIO Controllers
You can stream data from FPGA to RT and then to local disk at rates between 1.5 and 6.3 MB/s depending on the controller and file format.
Reference Applications for cRIO Waveform Acquisition
Ready-made application and higher level VIs for waveform acquisition and streaming from FPGA to RT on cRIO. This method achieves similar transfer rates to the previous article (1.64-7.37 MB/s).
The problem is related to the handshaking (or lack thereof) that you use between the FPGA and Host VI to determine when to read data in the host from the FPGA.
The FPGA VI starts to acquire data and will acquire data continuously at the rate specified by Loop Rate (ticks). The first time through the loop it will also set the Data Read 0 and Acquisition On flags to true.
In the host VI you wait fro Data Ready 0 to be true once at the very beginning, but then you go into your main loop where you read the data from the FPGA and no longer check either of these flags. You read Acqusition On but you do not use it for anything in your program logic. At this point your main loop reads data from the FPGA at the rate specified by the Wait (us) parameter on the front panel of the host VI.
If Wait (us) and Freq Loop Rate (Hz) do not macth up, then you will read eitehr too many or to few data points, meeaning you will read the same data point more than once from the FPGA or yo iwll miss some data points altogether. In your case you FPGA Loop rate is set to 20 kHz (50 us) and your Wait time is set to 70006 us (14.3 Hz), so I expect that you are missing a lot of data in your host VI.
You need to synchronize the FPGA loop and the host loop to read all of the data points acquired by the FPGA. You can use one of the flags (Data Ready 0) that you have defined on the FPGA for this purpose. After reading a data point in the host VI, reset this flag to False from the host VI. In the same loop on your host VI before you read a data value form the FPGA, check the Data Ready 0 flag and wait for it to be True before reading the next data value. This will then synchronize your host VI loop with the FPGA acquisition loop.
However, your best solution is to use DMA instead of transferring data using the front panel indicators. In your example you are trying to acquire data at 20 kHz and transfer a data point every 50 us. On a cRIO 9012 controller this may be too much for the processor to handle in addition to all of the other code (reading/writing chart properties) you have in the same loop on the host VI. With DMA you define a FIFO between the FPGA and host that transfers data in the background from the FPGA to space allocated in the host memory. In the host VI you can read out blocks of data from the DMA FIFO so that you can read 20 points every 1 ms for example. This reduces the overhead in your host VI and you can transfer data much faster than using the front panel indicators.
Take a look at the cRIO DMA example to learn how to use this function.
C:\Program Files\National Instruments\LabVIEW 2009\examples\CompactRIO\FPGA Fundamentals\DMA\DMA Buffered Acquisition\DMA Buffered Acquisition - cRIO.lvproj
