FPGA multiple channels/cards/slots

[jeff_scharpf]

This is a rather general question so I'll try to be brief. I am planning on building my own "horsepower" test for electric tools using a cRIO. I've experimented with reading AC volts and current to calculate my own power factor, rms values, etc....

Now I'd like to expand and read several parameters simultaneously. Volts, Amps, Torque, RPM. I will use a transducer to convert the volts and amps to a 10v level, etc.. I will use the high speed digital card to read the RPM, and another transducer to read torque.

When I set this up, I will probably sample the volts/amps as fast as possible over a few line cycles (if AC) so I can calculate my own power factor and true watts.

My question is, as I add more inputs (torque, RPM, etc), can I keep all of my readings in sync? Will the FPGA read ALL cards at the same time? If not, is there a way to calculate the total "skew" of readings let's say between my voltage transducer to my torque transducer.

Iniditially I'll have volts/amps/torque all on one 9215 card, but I might add more 9215 cards to read other levels of volts/amps or other torque transducers.

The high speed digital card requires some time interval to calcluate a speed (I think), so this overall sample rate would end up being slower.

I thought maybe I could set a time, say 50 ms, that I update my volts/amps/watts/torque etc.... The goal is to keep all the readings as "lined up" as possible.

To compare, currently we have some home grown VB software that reads volts/amps/watts through the GPIB from a power analyzer, then reads the torque from a transducer, to the values I provide have a 40 to 80 ms "skew" between them.  Does this make sense? I'm trying to reduce that "skew".

In the end, this will become (hopefully) our system for testing horsepower and providing the graphs and all that fun stuff..

I hope this is clear. I apologize if it's not. I am going to be saving lots of $$ if I can use the cRIO to replace the current sytsem.

Advice/comments extremely appreciated!!

Regards,

Jeff

[Christian_L]

Using one cRIO system with multiple C series module will give you very good synchronization. In your case if you are using 9215 modules and you place all your channels in one I/O node on the FPGA diagram, all of the channels will be sampled simultaneously. The 9215 has a dedicated A-to-D convert for each channel. Some other modules such as the 9201 use multiplexing, so that there is a slight skew between measurements from different channels on the same module. But the skew on these modules is on the order of a few microseconds, not milliseconds or tens of milliseconds.

If you place digital channels in the same I/O node as the analog channels, the command for a measurement will be sent from the FPGA to each of the modules at the same time. Because the digital modules are typically faster and do not have a long conversion time, their measurement will typically be taken slightly before the analog modules. But again, this skew will be on the order of microsecnds and will be constant from one measurement cycle to the next.

BTW, thank you for all the details in posting your question. It makes providing an answer much easier.

[xseadog]

Hi

an anolog operation takes 171 ticks whilst an digital is only 1 tick!  Thus operating with a clock at 40 MHz means a difference between 4.275us compared to 25 ns

So the digital read can be delayed to occur 'simulatanously' with the analog operation.

xseadog