FPGA timing slow

[tophatjim]

We have a compact Rio FPGA cRIO-9072 device.

1 Analog out, 2 analog in, 1 SSR running.  My program runs great, however I cannot get the cycle time to update readings to go faster than about 1 second/cycle.

I'm running a host VI and the FPGA target VI.  The clock frequency is 40M.

I know this is not a lot of information but I can't find genericly how to control the update speed of this FPGA board. I'd like to update about 10-100 times as fast.

Any ideas?

Thanks,

tophatjim 

[Christian_L · Accepted solution]

Most likely the SSR is slowing down the speed of the loop on the FPGA. I assume you are using the 9485 module.

You should place the I/O nodes for your different modules in different loops so that your AI and AO can run faster. The updates of the SSR will still run slower in their own loop. 

[tophatjim]

Thank you very much.

I now understand the three timing engines and how to use them to control each module independently.  That was the problem and now things are trucking (going really fast).

Thank you for your help.