FPGA with 2 loops, each with different I/O channel counts, require the same amount of time (5440 ticks); loops are independent, i.e. not linked other than the fact that all channels are from the same C-series module.

[aetc]

I created a simple FPGA program that contains 2 seperate loops, one with just 1 I/O channel, the other with 12; however both loops show the same loop duration (5440 ticks) - I would expect due to parallelism that the loop with only 1 channel would run faster; all the channels however are from the same C-series module (9205: AI voltage) - otherwise there is no dependence between the loops; does the fact that the channels are from the same module defeat the parallelism, i.e. make the sample time = the slowest? i.e. to have true parallelism - would I have to have a seperate modules for the various channel groupings?

Before I had created several test programs each containing a single loop; in each program I had different channel counts to compare how long the I/O process took; the results I had were as follows: 1 channel took 1200 ticks; 5 channels took 1600 ticks, 10 channels took 3200, 15 channels took 4800; and 20 channels took 6444 ticks;

[crossrulz]

The communications with the C-series module is done over a SPI bus.  So there is a common path to get your measurements from that module.  Therefore the sample rate of your data is keeping your loops at the same rate.  You have a couple of options if you want these to be truely parallel.  The first is to use a second module.  The second would be to use a loop to read from the module and then use a FIFO or global variables to send the data to your other loops.

[aetc]

thanks!