Failed FPGA Compilation

[Joe D. · Accepted solution]

Hi Dave,

After speaking to a few people in R&D what is happening is when we call the Xilinx compiler, which maps the LabVIEW FPGA to actual parts on the hardware. We are passing a High to Synthesis Optimization Effort Level . It looks like the 9265 in the project is what is causing the recommended settings option to Timing Performance. Apparently, the 9265 requires "increased effort" to compile. That's why with our own projects we couldn't reproduce the failure, because we didn't add the 9265, which changes the default setting.

I recommend that you can work around this by changing the Default design strategy to Area by going to the FPGA target >> Xilinux Options.

Hope this helps and best of luck on your application

[dj143]

Hi Joe,

Changing the Xilinx options as suggested results in successful compilation.  I have since received the cRIO-9114 chassis and related hardware and have successfully gotten it to work.  Thank you for your help with this.

For future FPGA users, right-click on the FPGA Target in the project and select Properties >> Xilinx Options.  Uncheck Use recommended settings and set Map Overall Effort Level to Standard.  The Design Strategy field will automatically set to Custom.  This is what I did to get my project to compile.

Dave.