Flex RIO 5782 phase locking

[Sparrow1]

Hi,

I am currently using a FLEX RIO multi card system with 5782 front-end cards.

I lock the 250MHz adapter clocks to the crate 10MHz refernce clock.

One in ten programming/synchronisation occurances results in the 250MHz clocks "partially" locking. When this occurs the clocks dither a little, but not as in an unlocked manner.

The PLL Locked signal returns a valid signal, as if the PLL's are locked.

I suspect the clock synthesizer on the 5782 module gives the problem.

I wondered if anyone else has found this ?

Dave.

[David-A]

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I lock the 250MHz adapter clocks to the crate 10MHz refernce clock.

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Theres a typo there. I assume you mean you lock the 250MHz clock that you get from the internal oscillator to the to the PXI 10MHz clock that is routed through the iomodsynclock line. If this is what you mean then you'll want to make sure you have the 'Internal Clock PLL On (IoModSyncClock)' setting for the clock configuration selected.

If you have the10Mhz ref clock or the sample clock coming in through the CLK IN on the front panel of the 5782 then you'll need to select a different setting.

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 One in ten programming/synchronisation occurances results in the 250MHz clocks "partially" locking. When this occurs the clocks dither a little, but not as in an unlocked manner.

The PLL Locked signal returns a valid signal, as if the PLL's are locked.

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If the PLL locked signal is returning true then how are you able to determine that the clock synthesizer is only partially locked? Also how are you measuring the dither of the clock?

[Sparrow1]

Hi David-A,

I am using the ModIOSyncClock, and setting the User command register to 0 and User data(0) = 3

I am using the 250MHz clock domain in each FPGA with a divide by 4 counter, driving an output but on the HDMI front panel connector. These are not suitable for high speed output ideally, but they give me an indication.

Also, I have internal pulses sync'd to 250MHz, which i agan, take to the front panel. I also observe on the DAC outputs unsynchronised sine waves, which i generate internally and hope to synchronise.

I did have some success using the FPGA reset and run commands and i thought this had solved it, but when a new compile was made, the problem returned.

I have tried adding time delays between Initialise_done and the start of the clock sync command phase, but no joy i'm afraid.

Any suggestions would be greatly appreciated ....

Dave.

[dragon1]

Were you able to solve this problem?

I am curious what the observed partial locking looks like. Can you post some screenshots ?