FlexRIO (NI 5785) complex transmission

[isoarsk4]

Hi all,

I've been trying to get myself familiar with the NI 5785 IF transceiver and its possible applications for our research. The available documentation seems to be quite limited, and I am now reaching out to the community in case someone has had similar challenges.

The device has two channels -- four single-ended connectors in total, which I have connected in a loopback fashion. I am using the provided LabVIEW FPGA example project (GettingStarted_5785) and having trouble understanding the processing of I/Q data. Looking at the FPGA code, the transmitter side output is wired to ports named "ao0" and "ao1", which are fed to the IO-node. This seems to correspond with the output measured from the physical SMA connectors. The receiver side FPGA code takes two channels from the IO-node as input. The input samples are inserted to an I/Q-structure, where the Q-component is initialized as zero and the I-component consists of the actual samples. Why is this done this way and what exactly does the frequency shift VI do?

My goal would be to receive samples from a single connector (real signal), separate the I and Q components of the signal, and process/demodulate the I and Q samples in the host or FPGA code. Is this something that is supported and/or intended use of the device?

To summarize my confusion:

1. Has anyone successfully transmitted complex signals using FlexRIO devices? What was your application and how did you do it?
2. Does the transceiver always treat the I and Q samples separately, in separate wires?
3. If not, can I use existing functionality (FlexRIO API or something else) for the quadrature demodulation, or do I have to do it from scratch? How would I start to implement this in FPGA?

Any replies, comments or questions are more than welcome. Thank you!

[UMASO]

Hello, welcome to community.  PXIe-5785 is one of my favorite deivces.  

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@isoarsk4 wrote:

The input samples are inserted to an I/Q-structure, where the Q-component is initialized as zero and the I-component consists of the actual samples. Why is this done this way and what exactly does the frequency shift VI do?

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In the example, there are two data path for AI; one for no DSP and the other for DDC.  Through the data path with DDC, each of two AI channels are treated as a single real signal.  In this example, to digitally down-convert each real signal from AI 0 or AI 1, 16SPC data are placed to In-phase and Quadrature are all zeroed (treated as real signal).  Then, Frequency Shift VI does frequency shift by taking complex multiplications with complex sinusoids being generated inside of the VI.  After Frequency Shift, original real signal gets out as a complex signal, and that complex signal goes through integer decimation by two.  One caveat of this example is that this DDC process skips filtering between frequency shift and decimation.  

If you would like, you can use two AI channels as a pair of IQ signal.  

Hope this helps!  

[isoarsk4]

Hello,

Thank you for your reply!

So, if I understand correctly, the input from AI 0 or AI 1 is first treated as a real signal and the complex multiplication produces the Q-component. Is this Q-component the sine amplitude, or is it just a "side effect" of the frequency shifting? Would I just have to include the filtering in order to demodulate the real input from a single channel to I and Q?

Using two AI channels to transmit IQ signal is something I was able to do already. At this point I am maybe wondering whether I should be using a 90° hybrid or something similar. For example, if my real input signal is coming from an antenna (a single wire), would I be able to demodulate the signal to I and Q components using the transceiver alone?

Again, thank you for your help. This helps a lot!

[UMASO]

Glad that it helped!  My apologizes and let me modify my previous comment.  The half-band decimator after frequency shift actually implements FIR filter inside.  I was thinking other VI which does integer decimation without filter implementation.  Therefore, you can use the example as it is, it actually demonstrates homodyne receiver.  

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@isoarsk4 wrote:

So, if I understand correctly, the input from AI 0 or AI 1 is first treated as a real signal and the complex multiplication produces the Q-component. Is this Q-component the sine amplitude, or is it just a "side effect" of the frequency shifting? Would I just have to include the filtering in order to demodulate the real input from a single channel to I and Q?

Please look at section "2. Homodyne Receiver" of https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z0000019Y9TSAU&l=ja-JP

Inside Frequency Shift VI, DDS exists and it is mixed with the real signal from AI 0 or AI 1, as you say.  For the example, as I corrected my prvious post above, LPF and decimation follow after the frequency shift.  

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@isoarsk4 wrote:

Using two AI channels to transmit IQ signal is something I was able to do already. At this point I am maybe wondering whether I should be using a 90° hybrid or something similar. For example, if my real input signal is coming from an antenna (a single wire), would I be able to demodulate the signal to I and Q components using the transceiver alone?

You can refer to other example for further signal processing.  My recommendation is NI-USRP Simple Streaming with USRP-2945/2955.  It demonstrates an additional DDC with fractional decimator.  You can check that example by installing NI-USRP driver.  

 

As you mentioned in your first post, PXIe-5785 requires a certain amount of experiences on LV and LV FPGA, because its sampling rate can be categoryzed to high-speed. 

[UMASO]

Hi, I remembered that I once had a question similar to yours.  

https://forums.ni.com/t5/LabVIEW/Trying-to-get-I-and-Q-value-from-USRP-2955/td-p/3684940

I guess the person in the above post asked almost the same question as yours, though hardware is different.  

[isoarsk4]

Hi,

Thank you, this already answers a lot of the questions I had!

I know this is quite specific, but do you know if it would be possible to use only one output port on the transmitter side? The original FPGA code in the example project always steers the I and Q samples to different ports. I have (unsuccessfully) attempted to modify the FPGA code such that the output would be a sum of I and Q, transmitted from AO 0 (see the picture).

Another thing I am still unsure about is the receiver, more specifically the way the I and Q components are generated using the homodyne receiver architecture you mentioned. In the example project host LV code there is the option "IQ Enabled", which I interpret to transfer the decimated and frequency shifted I- and Q-components to the host. I am seeing the Q-component as zero, unless I specify some Hz value to the frequency shift. I am not able to grasp what exactly happens there.

I have to admit that this seems to require more FPGA programming expertise than I currently have. Regardless, thank you for the helpful responses.

[UMASO]

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@isoarsk4 wrote:

I have (unsuccessfully) attempted to modify the FPGA code such that the output would be a sum of I and Q, transmitted from AO 0 (see the picture).

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What does "Unsuccessfully" mean?  You can compile the example, but you do not observe signal as expected?  

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@isoarsk4 wrote:

I am seeing the Q-component as zero, unless I specify some Hz value to the frequency shift. I am not able to grasp what exactly happens there.

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When 0 is set to frequency offset, the signal mixed with AI 0 (or AI 1) has all 1s for I and all 0s for Q, so that no frequency shift occurs and incoming signal just like goes through frequency shift VI.  

[isoarsk4]

Hello,

Thank you for your time and effort!

I feel like I have to provide some clarification about our use case and what I am trying to achieve. We are trying to transmit an OFDM signal (or any other complex waveform). We generate the complex baseband symbols in the host code, feeding complex data to the FPGA (interleaved Re and Im components of the complex symbols). We are looking to receive I and Q samples, which we can feed back to the host code for further demodulation.

We have used USRPs before. In the case of USRPs, the I and Q samples are routed to separate IO-nodes in the FPGA code. The hardware combines the I and Q signals and we end up with a real signal that can be transmitted over-the-air, using a single antenna. On the receiver side the input consists of a single physical connector. The hardware downconverts, filters, decimates etc. the signal, and in the FPGA code we see two separate IO-nodes from which we get I and Q samples. These I and Q samples can be interpreted as Re and Im components of the original complex symbols we transmitted.

Is the FlexRIO 5785 transceiver capable of doing the same as we did using the USRP? Do we need additional hardware, such as an I/Q upconverter to combine the I and Q channels into one real signal, and an I/Q downconverter for producing I and Q signals we can feed to the FPGA using the two channels? Could we, in theory, transmit a signal over-the-air instead of the two wires for I and Q? Is the device only designed for baseband processing with the requirement for additional hardware?

When I said "unsuccesfully", I meant that I was able to compile, but not able to see the I and Q samples on the receiver side. As you mentioned, the example code demonstrates the homodyne receiver. Just to clarify: Is the homodyne functionality entirely implemented on the FPGA? Are the values from the input channels "AI 0, AI 1" just raw ADC values, without any relation to I/Q components?

[UMASO · Accepted solution]

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@isoarsk4 wrote:

Is the FlexRIO 5785 transceiver capable of doing the same as we did using the USRP? Do we need additional hardware, such as an I/Q upconverter to combine the I and Q channels into one real signal, and an I/Q downconverter for producing I and Q signals we can feed to the FPGA using the two channels? Could we, in theory, transmit a signal over-the-air instead of the two wires for I and Q? Is the device only designed for baseband processing with the requirement for additional hardware?

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PXIe-5785 does not have analog front-end circuits for RF upconversion / downconversion.  If the bandwidth of your signal is covered by 3.2GSps, you can use PXIe-5785 AD/DA along with digital up/down conversions on FPGA.  But again, since PXIe-5785 does not have analog front-end such as amplifier, attenuator, etc, you are required to have external circuits for over-the-air kind of thing.  

I guess, you would like to observe baseband signal (or demodulated data) from receiver side which is the same as the signal (or pre-modulated data) to transmitter-side, by looping back AO and AI of PXIe-5785.  I am sure it is possible, but it is not so easy as you may expect.  

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@isoarsk4 wrote:

When I said "unsuccesfully", I meant that I was able to compile, but not able to see the I and Q samples on the receiver side. As you mentioned, the example code demonstrates the homodyne receiver. Just to clarify: Is the homodyne functionality entirely implemented on the FPGA? Are the values from the input channels "AI 0, AI 1" just raw ADC values, without any relation to I/Q components?

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Yes, you are correct.  DSP path for AI in the example treats AI 0 or AI 1 as real signal, and this is same as homodyne receiver which is digitally  accomplished on FPGA.  However, you can use AI 0 and AI 1 as IQ pair by modifying processing on FPGA, which is different from the example.  

[isoarsk4]

Hi,

Thank you very much! You have helped us immensely, and things are a lot clearer now. 🙂

Our application requires over-the-air RF transmission. It is now clear that we need additional hardware for that. It is still unclear to us whether we can use the same external hardware for RF up/downconversion as with USRP. Our USRP is capable of over-the-air transmission, and thus it outputs a complex I/Q signal -- the output is from one port, and the external upconverter turns it into a high-frequency RF signal.

Would it be possible to do this I/Q mixing using the FPGA, or is the hardware inherently limited to using two separate output wires in the case of a complex signal? To be concrete: can we modify the FPGA code such that our baseband OFDM signal comes out from the AO 0 connector? If not, then I understand that we have to use different external hardware that takes I and Q as separate inputs for upconversion and produces separate I and Q in downconversion.