Has anyone implemented the SPI bus on a 7831R using Labview 2009? I

[mswalker]

I have been trying to get the SPI bus protocol (http://zone.ni.com/devzone/cda/tut/p/id/9117) to run on my PCI-7831R series device with no luck.  I have followed the directions on the 'Changing FPGA Targets' heading.  When I change the FPGA target to match my hardware, it seems as though the FPGA reference (FPGA Reference.ctl) is not getting passed correctly between the following files (FPGA SPI_Configure.vi, FPGA SPI_Read Write.vi, and Example_Host SPI Dual Port.vi).

The common error between all of the vi's is the following:

An internal software error has occurred. Contact National Instruments technical support at ni.com/support. Error details:
Error -61499 occurred at an unidentified location

Possible reason(s):

LabVIEW FPGA:  An internal software error in the LabVIEW FPGA Module has occurred.  Please contact National Instruments technical support at ni.com/support.

Additional Information: The target class configuration does not match the target class in the bitfile. This could be caused by using the same VI in different targets. Try renaming your target.

Has anyone successfully pulled this off?  Any suggestions would be greatly appreciated.

[Donovan_B · Accepted solution]

There are a couple things you will need to do to move this bus to a different target.

1. The first thing you will need to do is create a new target in the project or create a new project with the target type you want to compile for.  You will need to copy the FIFOs, and any IO that you are going to use under this target.
2. The IO of the Single-Board RIO device in the example project will not be the same as the IO types on the R Series board.  Specifically, the IO lines have different properties and methods associated with them and the PORTs of an sbRIO are 10 bits wide while the R Series ports are 8 bits.  To rectify this:
   1. Make sure you have the IO set up for Boolean values for SCLK, MOSI, and MISO and a Port set for CS.
   2. Open FPGA SPI_SPI_Port.vi and change the IO type of each of the controls in the FPGA IO cluster.  To do this, right-click each IO Name control and choose Configure I/O Type…  Choose the corresponding I/O in your project from the tree on the left side of the dialog that will appear and then click Replace All.  This will set the IO type for that control to match the type defined in your project.  Save the port VI.
   3. In the top-level FPGA VI, locate all of the port subVIs.  For each of these port VIs, delete the FPGA IO cluster constant and then right-click on the FPGA IO terminal and Create»Constant.  This will create a new cluster with the correct IO types and you should be able to select the FPGA IO contained within your project.
   4. Save and recompile the top-level FPGA VI.
3. In the host VI, Configure the Open FPGA VI Reference to be bound to either the newly compiled bitfile or the top-level FPGA VI under your new target.  Make sure this reference is bound to the FPGA Reference.ctl file in the project.  All the subVIs share this typedef control, so if you are binding to a different control, the subVIs will need to be updated manually.

You should now be able to use the SPI bus with your target.

[mswalker]

Donovan,

I Can't thank you enough for your suggestions.  I got it up and running last night.  Before my question I was trying to change the I/O types, but apparently was not doing so correctly.  I am still learning the ropes of programming FPGA's via LabVIEW - so thankfully there are folks like yourself out there that can point me in the right direction.  Thanks again!

[Donovan_B]

No problem.  I'm glad you were able to get everything running.  Hopefully, we'll be able to get some more information into that document that details more about changing targets.  If you have any more feedback about the document, let me know as well so we can continue to make it better.  And if you run across any more issues, we're always here to help.

[Eletrostatic]

Hi Guys.

I am using the same example with the 7813R and have a few issues I need to resolve.

Firstly I have 3 SPI channels one of which uses a DMA. I have duplicated the ports and interfaces within the FPGA so that I have three seperate multiplexers. How can I put all of my CS and SPI I\0 lines onto one port? The example uses 2 ports one for SPI lines and one for CS's. I really  need all signals on one port.

Secondly how can I increase the number of Chip selects on the port? Example states only one CS can handle 8 slaves. How can I exapand this?

Thanks, I hope someone can assist me.

Pete

[smithd]

Hi,

One suggestion I have for you is to take a look at the spi_single_port example on the page listed above. As I am reading your question, you just need to merge the two examples together. Single_port_example uses a 9401, while spi_dual_port_example uses an SB rio with 3 separate ports. From that documentation, it seems like you are limited by your combined CS/SPI count. Each SPI channel requires 3 DIO lines, and then you can fill the rest of the port with CS lines. Past that, it seems you are limited by hardware.

As a side note, I would highly recommend creating a new thread. While this thread might have the same name you would choose for your issue, the topics discussed seem to be completely different. Additionally, not as many users are going to look at a forum post that is two years old.

Thanks,

D Smith

[Eletrostatic]

Hi,

Yes I am using the one above. I have created the question here http://forums.ni.com/t5/LabVIEW/SPI-example-questions/m-p/1424960. If you can take a look.

I will take a look at the single port example and try to merge the I/O. I'll get back to you.

Thanks

Pete

[Eletrostatic]

Hi,

One of the problems is when I try to change the I/O config for the CS. using Ports seems to be ok. But when I use for example DIO5 it complains that the data type is a mismatch. because the design expects an I/O with only Boolean attributes.

How to change this?

Thanks

Peter

[smithd]

Okay, I think I have a better idea of what you're trying to do. One unclear thing is how the DMA is coming in to it, as my impression was that the FPGA would send data faster than your realtime controller would be able to write it, but I'll leave that aspect up to you. Another question I had is, in your other thread, what you mean by "on the same bus"--I'm not entirely sure what you mean by that. Finally, I am not sure why you need these to all be on the same port.

After looking in to SPI some more, my understanding is that, if you want 32 slaves, you need a 5 bit mux chip to route the CS channel to the correct slave. This, in turn, requires 5 DIO lines to control the MUX. At the same time, each SPI set takes 3 DIO lines. That is, any SPI set up with one master and 32 slaves requires, at minimum, a single port to operate. The normal 8-slave limitation comes from this requirement that each slave has its own CS line. Even this may be oversimplifying the situation, but it seems possible in theory.
this file, on page 8, is a good image to describe why they must be on separate ports.

Now they I better understand your requirements, I don't believe what you want to do is possible. Think about your requirements some more, along with the requirements above, and let me know if you have further questions. And definitely feel free to let me know if I'm wrong, and we can look into this some more.

Thanks,

D Smith

[Eletrostatic]

Hi, Firstly the architecture of our system is taking a little understanding on my part. Basically I think I finally start to understand what our system designers are trying to do.

We have 3 SPI busses, which only have only 1 CS each. One SPI bus is used to control a CPLD (like a mux, SPI messages contain CS selection information)) to expand the CS for the devices on the other 2 SPI buses.

So now I have made the addressing of NI's driver to a boolean state (Will always be on) and the CS active state's within the HOST.VI are used to select the CS prior to the message been written with the write control also in the HOST.VI. (at least this is what I assume "CS active status" is.

We tested the speed of the logically changes between the HOST and the FGPA's I/0 and its about 750ns. Which should be fast enough for our needs.

Monday I plan to compile and test. So I will report back if I get any issues.

Thanks for your help.

P.S. DMA is used to only read from the FPGA card, as we have so many boards. Messages are auto incremented addressed.