Hi
I am using a cRIO-9004 together with a lot of I/O modules and an FPGA.
I have a VI running on my FPGA sending all my signals to the I/O modules and my RealTime VI. The realtime VI has two timed loops, a deterministic GIANT loop (approx 100Hz) processing signals and controlling a lot of actuators via the FPGA, the second loop is taking car of the data aquisition (10 Hz). The Real Time VI is using shared variables to communicate with a host VI running on my laptop, where I manually can interact with the system and read out values in graphs.
In my system i would like to generate (and recieve )a 10V signal via my Analog Output (and input) module. The signal is to be a sine wave, but it would be nice to alter it to e.g. a triangle. I would like to be able to change to frequency and ampltude of this signal to a maximum of about 80-100kHz, or as high as possible.
I guess that the Realtime VI probably is running to slow to generate this signal with a proper resolution, so left is the FPGA which probably can do this, but how? And how do I save the analog input signal when I only have "slow" timed loops on my RT, can the FPGA also do this.
I'm not sure how to carry this out, if I have to find an extra device to handle this high frequency generation and datalogging or if i'm able to do it together with all my other activities on the cRIO?
Regards
soeren
