How can I slow down the sample rate of 5781？

[xlwrn50x]

I’m using the 5781 and its sample rate is 100Ms/s,I want to slow it down and I already know that the I/O module clock will always be 100MHz so I can't change it.Then I use the 40MHz clock on the fpga in sctl,although I can slow it down but it is not synchronous with the I/O clock,which cause a problem:the whole shape of wave is corret,but at some point the value goes straight up,which looks like a burr(and I don't know why),and this causes the envelop of the wave also has burrs,which is not what I want.So,what I want is to slow down the I/O clock to lower the sample rate,any ideas?Thanks in advance.

[BillTür]

Could you maybe post or send me a screenshot of these burrs? I think I'm experiencing something similar and I am in contact with the NI tech support.

This behaviour is definitely not acceptable and according to NI documentation it shouldn't be a problem to use other clocks for data acquisition (in my case 60 MHz).

[xlwrn50x]

It's hard to get a screenshot because its duration is very short.I recently read some papers and find out the reason:if you are using the I/O clock the data will be acquired at the middle of the clock pulse,but if you are using another clock the data won't be read at the middle,which will cause some random value.Now I'm trying to extract one point from every ten acquired data,I hope it will work.

Hope you find these useful.