07-22-2005 10:09 AM
07-25-2005 11:39 PM
The VI running on the FPGA can't directly talk to the serial port like it can with cRIO I/O modules. Rather, the serial port is intended to communicate with the Real-Time VI running on the 9002/9004. It's also useful for debugging using serial redirect if the controller ever has problems booting up. But for your purposes, it sounds like you will need to pass data back and forth between the RT VI and the FPGA VI using the Read/Write Control found on the block diagram under All Functions>>FPGA Interface>>"Read/Write Control".
For examples of how this communication between RT VI and FPGA VI using the Read/Write Control is set-up, take a look at the shipping examples in LabVIEW under Help>>Find Examples, then browse to the folder Toolkits and Modules>>FPGA>>Fundamentals>>Synchronizing. This should be a good starting point.