01-12-2007 04:22 AM
01-14-2007 12:57 PM
Ian,
I have been a little disappointed at what will fit on the 1M gate CRIO, but your application seems pretty small, relatively speaking, so I would think the 1M gate would work for you. As long as you are careful with your FPGA code, use DMA FIFO's for the data transfer, you should be ok. Since you don't need to run the FPGA really fast, you can change the way it optimizes as it compiles - using space instead of speed for the criteria. If you run into problems, you can always move the PID loops up to RT, rather than on the FPGA, which is what I have done in the past.
So far, I have found that programming with the CRIO is a balancing act between the RT and the FPGA code to not load either one down too much. It can be tricky, that is for sure. But, if you can get away from the cost of the 3M gate, it is probably worth it.
Hope this helps,
Rob
01-15-2007 02:02 AM
Rob
Thanks for the information, your tips will help me get started and avoid possible pitfalls. The next few months are going to be an interesting learning curve! At least I can go ahead now and put in my order for the hardware with a bit more confidence.
Thanks again
Ian